Search

Kretelia Graham

Examiner (ID: 7064)

Most Active Art Unit
2827
Art Unit(s)
2825, 2615, 2817, 2827
Total Applications
682
Issued Applications
565
Pending Applications
4
Abandoned Applications
116

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5090613 [patent_doc_number] => 20070230252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'Row selector for a semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/726726 [patent_app_country] => US [patent_app_date] => 2007-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 15973 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20070230252.pdf [firstpage_image] =>[orig_patent_app_number] => 11726726 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/726726
Row selector for a semiconductor memory device Mar 20, 2007 Abandoned
Array ( [id] => 4958965 [patent_doc_number] => 20080273389 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-06 [patent_title] => 'Flash memory cells, NAND cell units, methods of forming NAND cell units, and methods of programming NAND cell unit strings' [patent_app_type] => utility [patent_app_number] => 11/726320 [patent_app_country] => US [patent_app_date] => 2007-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5784 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0273/20080273389.pdf [firstpage_image] =>[orig_patent_app_number] => 11726320 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/726320
Flash memory cells, NAND cell units, methods of forming NAND cell units, and methods of programming NAND cell unit strings Mar 20, 2007 Abandoned
Array ( [id] => 275295 [patent_doc_number] => 07561465 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-14 [patent_title] => 'Methods and systems for recovering data in a nonvolatile memory array' [patent_app_type] => utility [patent_app_number] => 11/724774 [patent_app_country] => US [patent_app_date] => 2007-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4014 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/561/07561465.pdf [firstpage_image] =>[orig_patent_app_number] => 11724774 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/724774
Methods and systems for recovering data in a nonvolatile memory array Mar 15, 2007 Issued
Array ( [id] => 4763824 [patent_doc_number] => 20080175035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-24 [patent_title] => 'Non-volatile resistance changing for advanced memory applications' [patent_app_type] => utility [patent_app_number] => 11/724788 [patent_app_country] => US [patent_app_date] => 2007-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 11347 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20080175035.pdf [firstpage_image] =>[orig_patent_app_number] => 11724788 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/724788
Non-volatile resistance changing for advanced memory applications Mar 15, 2007 Issued
Array ( [id] => 4738527 [patent_doc_number] => 20080232179 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-25 [patent_title] => 'Circuit, system and method for controlling read latency' [patent_app_type] => utility [patent_app_number] => 11/724910 [patent_app_country] => US [patent_app_date] => 2007-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7282 [patent_no_of_claims] => 63 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20080232179.pdf [firstpage_image] =>[orig_patent_app_number] => 11724910 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/724910
Circuit, system and method for controlling read latency Mar 14, 2007 Issued
Array ( [id] => 275313 [patent_doc_number] => 07561483 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-14 [patent_title] => 'Internally asymmetric method for evaluating static memory cell dynamic stability' [patent_app_type] => utility [patent_app_number] => 11/685904 [patent_app_country] => US [patent_app_date] => 2007-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4884 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/561/07561483.pdf [firstpage_image] =>[orig_patent_app_number] => 11685904 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/685904
Internally asymmetric method for evaluating static memory cell dynamic stability Mar 13, 2007 Issued
Array ( [id] => 327710 [patent_doc_number] => 07515491 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-07 [patent_title] => 'Method for evaluating leakage effects on static memory cell access time' [patent_app_type] => utility [patent_app_number] => 11/685905 [patent_app_country] => US [patent_app_date] => 2007-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4898 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/515/07515491.pdf [firstpage_image] =>[orig_patent_app_number] => 11685905 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/685905
Method for evaluating leakage effects on static memory cell access time Mar 13, 2007 Issued
Array ( [id] => 346173 [patent_doc_number] => 07499365 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-03-03 [patent_title] => 'Dual port PLD embedded memory block to support read-before-write in one clock cycle' [patent_app_type] => utility [patent_app_number] => 11/683072 [patent_app_country] => US [patent_app_date] => 2007-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4514 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/499/07499365.pdf [firstpage_image] =>[orig_patent_app_number] => 11683072 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/683072
Dual port PLD embedded memory block to support read-before-write in one clock cycle Mar 6, 2007 Issued
Array ( [id] => 4987269 [patent_doc_number] => 20070153607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-05 [patent_title] => 'Semiconductor memory device changing refresh interval depending on temperature' [patent_app_type] => utility [patent_app_number] => 11/713029 [patent_app_country] => US [patent_app_date] => 2007-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5835 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20070153607.pdf [firstpage_image] =>[orig_patent_app_number] => 11713029 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/713029
Semiconductor memory device changing refresh interval depending on temperature Mar 1, 2007 Issued
Array ( [id] => 76558 [patent_doc_number] => 07751223 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-06 [patent_title] => 'Magnetic memory devices using magnetic domain motion' [patent_app_type] => utility [patent_app_number] => 11/707002 [patent_app_country] => US [patent_app_date] => 2007-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 9475 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/751/07751223.pdf [firstpage_image] =>[orig_patent_app_number] => 11707002 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/707002
Magnetic memory devices using magnetic domain motion Feb 15, 2007 Issued
Array ( [id] => 4447748 [patent_doc_number] => 07864576 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-04 [patent_title] => 'Nonvolatile memory cell array architecture for high speed reading' [patent_app_type] => utility [patent_app_number] => 11/707130 [patent_app_country] => US [patent_app_date] => 2007-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5348 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/864/07864576.pdf [firstpage_image] =>[orig_patent_app_number] => 11707130 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/707130
Nonvolatile memory cell array architecture for high speed reading Feb 15, 2007 Issued
Array ( [id] => 94664 [patent_doc_number] => 07738278 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-15 [patent_title] => 'Magnetic memory device using magnetic domain motion' [patent_app_type] => utility [patent_app_number] => 11/706988 [patent_app_country] => US [patent_app_date] => 2007-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 8610 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/738/07738278.pdf [firstpage_image] =>[orig_patent_app_number] => 11706988 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/706988
Magnetic memory device using magnetic domain motion Feb 15, 2007 Issued
Array ( [id] => 114187 [patent_doc_number] => 07719899 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-18 [patent_title] => 'Circuits, systems and methods for driving high and low voltages on bit lines in non-volatile memory' [patent_app_type] => utility [patent_app_number] => 11/705896 [patent_app_country] => US [patent_app_date] => 2007-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3328 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/719/07719899.pdf [firstpage_image] =>[orig_patent_app_number] => 11705896 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/705896
Circuits, systems and methods for driving high and low voltages on bit lines in non-volatile memory Feb 12, 2007 Issued
Array ( [id] => 5111683 [patent_doc_number] => 20070195598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'Accessing semiconductor memory device according to an address and additional access information' [patent_app_type] => utility [patent_app_number] => 11/705485 [patent_app_country] => US [patent_app_date] => 2007-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4075 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20070195598.pdf [firstpage_image] =>[orig_patent_app_number] => 11705485 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/705485
Accessing semiconductor memory device according to an address and additional access information Feb 11, 2007 Issued
Array ( [id] => 5067976 [patent_doc_number] => 20070189077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-16 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/704934 [patent_app_country] => US [patent_app_date] => 2007-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6334 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20070189077.pdf [firstpage_image] =>[orig_patent_app_number] => 11704934 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/704934
Semiconductor memory device Feb 11, 2007 Abandoned
Array ( [id] => 7704059 [patent_doc_number] => 08089822 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-01-03 [patent_title] => 'On-chip power-measurement circuit using a low drop-out regulator' [patent_app_type] => utility [patent_app_number] => 11/705288 [patent_app_country] => US [patent_app_date] => 2007-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2702 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/089/08089822.pdf [firstpage_image] =>[orig_patent_app_number] => 11705288 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/705288
On-chip power-measurement circuit using a low drop-out regulator Feb 11, 2007 Issued
Array ( [id] => 5335798 [patent_doc_number] => 20090052262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-26 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/278730 [patent_app_country] => US [patent_app_date] => 2007-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 17432 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20090052262.pdf [firstpage_image] =>[orig_patent_app_number] => 12278730 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/278730
SEMICONDUCTOR MEMORY DEVICE Feb 5, 2007 Abandoned
Array ( [id] => 5251800 [patent_doc_number] => 20070133256 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-14 [patent_title] => 'Integrated circuit with a memory of reduced consumption' [patent_app_type] => utility [patent_app_number] => 11/701012 [patent_app_country] => US [patent_app_date] => 2007-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3596 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20070133256.pdf [firstpage_image] =>[orig_patent_app_number] => 11701012 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/701012
Integrated circuit with a memory of reduced consumption Jan 31, 2007 Abandoned
Array ( [id] => 906107 [patent_doc_number] => 07336555 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-26 [patent_title] => 'Refresh control circuit of pseudo SRAM' [patent_app_type] => utility [patent_app_number] => 11/619855 [patent_app_country] => US [patent_app_date] => 2007-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 6661 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/336/07336555.pdf [firstpage_image] =>[orig_patent_app_number] => 11619855 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/619855
Refresh control circuit of pseudo SRAM Jan 3, 2007 Issued
Array ( [id] => 164715 [patent_doc_number] => 07672178 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-02 [patent_title] => 'Dynamic adaptive read return of DRAM data' [patent_app_type] => utility [patent_app_number] => 11/648855 [patent_app_country] => US [patent_app_date] => 2006-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 4291 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/672/07672178.pdf [firstpage_image] =>[orig_patent_app_number] => 11648855 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/648855
Dynamic adaptive read return of DRAM data Dec 28, 2006 Issued
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