
Kretelia Graham
Examiner (ID: 7064)
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2825, 2615, 2817, 2827 |
| Total Applications | 682 |
| Issued Applications | 565 |
| Pending Applications | 4 |
| Abandoned Applications | 116 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 134054
[patent_doc_number] => 07701765
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-04-20
[patent_title] => 'Non-volatile multilevel memory cell programming'
[patent_app_type] => utility
[patent_app_number] => 11/646658
[patent_app_country] => US
[patent_app_date] => 2006-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 8545
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/701/07701765.pdf
[firstpage_image] =>[orig_patent_app_number] => 11646658
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/646658 | Non-volatile multilevel memory cell programming | Dec 27, 2006 | Issued |
Array
(
[id] => 4750902
[patent_doc_number] => 20080158973
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-03
[patent_title] => 'COMPLETE WORD LINE LOOK AHEAD WITH EFFICIENT DATA LATCH ASSIGNMENT IN NON-VOLATILE MEMORY READ OPERATIONS'
[patent_app_type] => utility
[patent_app_number] => 11/617544
[patent_app_country] => US
[patent_app_date] => 2006-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 21849
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0158/20080158973.pdf
[firstpage_image] =>[orig_patent_app_number] => 11617544
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/617544 | Complete word line look ahead with efficient data latch assignment in non-volatile memory read operations | Dec 27, 2006 | Issued |
Array
(
[id] => 5061656
[patent_doc_number] => 20070223295
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-09-27
[patent_title] => 'FLASH MEMORY DEVICE HAVING A FUNCTION FOR REDUCING DATA INPUT ERROR AND METHOD OF INPUTTING THE DATA IN THE SAME'
[patent_app_type] => utility
[patent_app_number] => 11/617406
[patent_app_country] => US
[patent_app_date] => 2006-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5114
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0223/20070223295.pdf
[firstpage_image] =>[orig_patent_app_number] => 11617406
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/617406 | Flash memory device having a function for reducing data input error and method of inputting the data in the same | Dec 27, 2006 | Issued |
Array
(
[id] => 7592287
[patent_doc_number] => 07652918
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-01-26
[patent_title] => 'Retention margin program verification'
[patent_app_type] => utility
[patent_app_number] => 11/617546
[patent_app_country] => US
[patent_app_date] => 2006-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 13
[patent_no_of_words] => 7439
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/652/07652918.pdf
[firstpage_image] =>[orig_patent_app_number] => 11617546
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/617546 | Retention margin program verification | Dec 27, 2006 | Issued |
Array
(
[id] => 4750938
[patent_doc_number] => 20080159009
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-03
[patent_title] => 'METHOD, APPARATUS, AND SYSTEM FOR IMPROVED ERASE OPERATION IN FLASH MEMORY'
[patent_app_type] => utility
[patent_app_number] => 11/617516
[patent_app_country] => US
[patent_app_date] => 2006-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6056
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0159/20080159009.pdf
[firstpage_image] =>[orig_patent_app_number] => 11617516
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/617516 | Method, apparatus, and system for improved erase operation in flash memory | Dec 27, 2006 | Issued |
Array
(
[id] => 4691995
[patent_doc_number] => 20080084766
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-04-10
[patent_title] => 'FLASH MEMORY DEVICE AND METHOD OF ERASING MEMORY CELL BLOCK IN THE SAME'
[patent_app_type] => utility
[patent_app_number] => 11/617670
[patent_app_country] => US
[patent_app_date] => 2006-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 3368
[patent_no_of_claims] => 17
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0084/20080084766.pdf
[firstpage_image] =>[orig_patent_app_number] => 11617670
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/617670 | Flash memory device and method of erasing memory cell block in the same | Dec 27, 2006 | Issued |
Array
(
[id] => 4750943
[patent_doc_number] => 20080159014
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-03
[patent_title] => 'SRAM MEMORY DEVICE WITH IMPROVED WRITE OPERATION AND METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 11/617336
[patent_app_country] => US
[patent_app_date] => 2006-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5891
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 10
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0159/20080159014.pdf
[firstpage_image] =>[orig_patent_app_number] => 11617336
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/617336 | SRAM memory device with improved write operation and method thereof | Dec 27, 2006 | Issued |
Array
(
[id] => 360733
[patent_doc_number] => 07486566
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-02-03
[patent_title] => 'Methods, apparatus, and systems for flash memory bit line charging'
[patent_app_type] => utility
[patent_app_number] => 11/617502
[patent_app_country] => US
[patent_app_date] => 2006-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6031
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 5
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/486/07486566.pdf
[firstpage_image] =>[orig_patent_app_number] => 11617502
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/617502 | Methods, apparatus, and systems for flash memory bit line charging | Dec 27, 2006 | Issued |
Array
(
[id] => 4750901
[patent_doc_number] => 20080158972
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-03
[patent_title] => 'METHOD OF CONTROLLING BITLINE BIAS VOLTAGE'
[patent_app_type] => utility
[patent_app_number] => 11/617514
[patent_app_country] => US
[patent_app_date] => 2006-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 3734
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[pdf_file] => publications/A1/0158/20080158972.pdf
[firstpage_image] =>[orig_patent_app_number] => 11617514
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/617514 | METHOD OF CONTROLLING BITLINE BIAS VOLTAGE | Dec 27, 2006 | Abandoned |
Array
(
[id] => 4750861
[patent_doc_number] => 20080158932
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-03
[patent_title] => 'Memory having bit line with resistor(s) between memory cells'
[patent_app_type] => utility
[patent_app_number] => 11/648399
[patent_app_country] => US
[patent_app_date] => 2006-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5686
[patent_no_of_claims] => 20
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0158/20080158932.pdf
[firstpage_image] =>[orig_patent_app_number] => 11648399
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/648399 | Memory having bit line with resistor(s) between memory cells | Dec 27, 2006 | Issued |
Array
(
[id] => 4750878
[patent_doc_number] => 20080158949
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-03
[patent_title] => 'SYSTEMS FOR COMPLETE WORD LINE LOOK AHEAD WITH EFFICIENT DATA LATCH ASSIGNMENT IN NON-VOLATILE MEMORY READ OPERATIONS'
[patent_app_type] => utility
[patent_app_number] => 11/617550
[patent_app_country] => US
[patent_app_date] => 2006-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
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[patent_no_of_words] => 21846
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[pdf_file] => publications/A1/0158/20080158949.pdf
[firstpage_image] =>[orig_patent_app_number] => 11617550
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/617550 | Systems for complete word line look ahead with efficient data latch assignment in non-volatile memory read operations | Dec 27, 2006 | Issued |
Array
(
[id] => 124288
[patent_doc_number] => 07710799
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-05-04
[patent_title] => 'Circuit for generating data strobe in DDR memory device, and method therefor'
[patent_app_type] => utility
[patent_app_number] => 11/611922
[patent_app_country] => US
[patent_app_date] => 2006-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/710/07710799.pdf
[firstpage_image] =>[orig_patent_app_number] => 11611922
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/611922 | Circuit for generating data strobe in DDR memory device, and method therefor | Dec 17, 2006 | Issued |
Array
(
[id] => 4982992
[patent_doc_number] => 20070087550
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-04-19
[patent_title] => 'LOW-VOLTAGE SINGLE-LAYER POLYSILICON EEPROM MEMORY CELL'
[patent_app_type] => utility
[patent_app_number] => 11/548512
[patent_app_country] => US
[patent_app_date] => 2006-10-11
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0087/20070087550.pdf
[firstpage_image] =>[orig_patent_app_number] => 11548512
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/548512 | LOW-VOLTAGE SINGLE-LAYER POLYSILICON EEPROM MEMORY CELL | Oct 10, 2006 | Abandoned |
Array
(
[id] => 1078002
[patent_doc_number] => 07616521
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-11-10
[patent_title] => 'Semiconductor memory device selectively enabling address buffer according to data output'
[patent_app_type] => utility
[patent_app_number] => 11/529260
[patent_app_country] => US
[patent_app_date] => 2006-09-29
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[firstpage_image] =>[orig_patent_app_number] => 11529260
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/529260 | Semiconductor memory device selectively enabling address buffer according to data output | Sep 28, 2006 | Issued |
Array
(
[id] => 4447707
[patent_doc_number] => 07864557
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-01-04
[patent_title] => 'Flexible OTP sector protection architecture for flash memories'
[patent_app_type] => utility
[patent_app_number] => 11/529158
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[pdf_file] => patents/07/864/07864557.pdf
[firstpage_image] =>[orig_patent_app_number] => 11529158
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/529158 | Flexible OTP sector protection architecture for flash memories | Sep 27, 2006 | Issued |
Array
(
[id] => 5134871
[patent_doc_number] => 20070076500
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-04-05
[patent_title] => 'Semiconductor memory device'
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[pdf_file] => publications/A1/0076/20070076500.pdf
[firstpage_image] =>[orig_patent_app_number] => 11528532
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/528532 | Semiconductor memory device | Sep 27, 2006 | Abandoned |
Array
(
[id] => 5170296
[patent_doc_number] => 20070070727
[patent_country] => US
[patent_kind] => A1
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[patent_title] => 'Semiconductor memory device including reset control circuit'
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Array
(
[id] => 850446
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Array
(
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[patent_title] => 'Non-volatile semiconductor memory device using adjacent bit lines for data transmission and method of driving the same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/528924 | Non-volatile semiconductor memory device using adjacent bit lines for data transmission and method of driving the same | Sep 27, 2006 | Issued |
Array
(
[id] => 5153141
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[patent_title] => 'Method for detecting data strobe signal'
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[patent_app_number] => 11/528639
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[pdf_file] => publications/A1/0036/20070036023.pdf
[firstpage_image] =>[orig_patent_app_number] => 11528639
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/528639 | Method for detecting data strobe signal | Sep 27, 2006 | Issued |