Search

Kretelia Graham

Examiner (ID: 19041, Phone: (571)272-5055 , Office: P/2825 )

Most Active Art Unit
2827
Art Unit(s)
2825, 2827, 2615, 2817
Total Applications
683
Issued Applications
562
Pending Applications
12
Abandoned Applications
115

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18950770 [patent_doc_number] => 11894073 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-06 [patent_title] => Proactive refresh of edge data word line for semi-circle drain side select gate [patent_app_type] => utility [patent_app_number] => 17/487665 [patent_app_country] => US [patent_app_date] => 2021-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 14657 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17487665 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/487665
Proactive refresh of edge data word line for semi-circle drain side select gate Sep 27, 2021 Issued
Array ( [id] => 18285547 [patent_doc_number] => 20230101019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => MTIGATING NEIGHBOR INTERFERENCE TO SELECT GATES IN 3D MEMORY [patent_app_type] => utility [patent_app_number] => 17/484218 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23679 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17484218 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/484218
Mitigating neighbor interference to select gates in 3D memory Sep 23, 2021 Issued
Array ( [id] => 18258543 [patent_doc_number] => 20230085583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => THREE DIMENSION MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/477229 [patent_app_country] => US [patent_app_date] => 2021-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8055 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17477229 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/477229
THREE DIMENSION MEMORY DEVICE Sep 15, 2021 Abandoned
Array ( [id] => 18255892 [patent_doc_number] => 20230082931 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => MEMORY CIRCUIT STRUCTURE WITH SUPPLY VOLTAGE TRANSMITTED VIA WORD LINE [patent_app_type] => utility [patent_app_number] => 17/447841 [patent_app_country] => US [patent_app_date] => 2021-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4477 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17447841 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/447841
Memory circuit structure with supply voltage transmitted via word line Sep 15, 2021 Issued
Array ( [id] => 18242114 [patent_doc_number] => 20230074425 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => Adaptive Current Mirror Circuit for Current Shaping with Temperature [patent_app_type] => utility [patent_app_number] => 17/467910 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9895 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17467910 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/467910
Adaptive current mirror circuit for current shaping with temperature Sep 6, 2021 Issued
Array ( [id] => 17886153 [patent_doc_number] => 20220301630 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/464297 [patent_app_country] => US [patent_app_date] => 2021-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12596 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17464297 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/464297
Semiconductor storage device including a voltage generator for applying first and second intermediate voltages to an adjacent word line in a program operation Aug 31, 2021 Issued
Array ( [id] => 18230266 [patent_doc_number] => 20230069260 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => SUB-BLOCK PROGRAMMING MODE WITH MULTI-TIER BLOCK [patent_app_type] => utility [patent_app_number] => 17/461922 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22570 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17461922 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/461922
Sub-block programming mode with multi-tier block Aug 29, 2021 Issued
Array ( [id] => 17854929 [patent_doc_number] => 20220284972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/459712 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14333 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17459712 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/459712
Semiconductor storage device comprising a control circuit for changing a rate of increase of a voltage applied to non-selected word lines Aug 26, 2021 Issued
Array ( [id] => 18528536 [patent_doc_number] => 11715534 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-01 [patent_title] => Semiconductor storage device capable of selectively erasing data [patent_app_type] => utility [patent_app_number] => 17/459441 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 25 [patent_no_of_words] => 19675 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17459441 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/459441
Semiconductor storage device capable of selectively erasing data Aug 26, 2021 Issued
Array ( [id] => 17566311 [patent_doc_number] => 20220130460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => WORD LINE DRIVE CIRCUIT AND DYNAMIC RANDOM ACCESS MEMORY [patent_app_type] => utility [patent_app_number] => 17/412363 [patent_app_country] => US [patent_app_date] => 2021-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3827 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17412363 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/412363
Word line drive circuit and dynamic random access memory Aug 25, 2021 Issued
Array ( [id] => 18623591 [patent_doc_number] => 11756645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Control circuit, memory system and control method [patent_app_type] => utility [patent_app_number] => 17/408500 [patent_app_country] => US [patent_app_date] => 2021-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 9221 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17408500 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/408500
Control circuit, memory system and control method Aug 22, 2021 Issued
Array ( [id] => 17854919 [patent_doc_number] => 20220284962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/445614 [patent_app_country] => US [patent_app_date] => 2021-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22460 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17445614 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/445614
MEMORY SYSTEM Aug 22, 2021 Abandoned
Array ( [id] => 18839976 [patent_doc_number] => 11848055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-19 [patent_title] => Asynchronous access multi-plane solid-state memory [patent_app_type] => utility [patent_app_number] => 17/406346 [patent_app_country] => US [patent_app_date] => 2021-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 10706 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17406346 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/406346
Asynchronous access multi-plane solid-state memory Aug 18, 2021 Issued
Array ( [id] => 18935232 [patent_doc_number] => 11887670 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-30 [patent_title] => Controlling bit line pre-charge voltage separately for multi-level memory cells and single-level memory cells to reduce peak current consumption [patent_app_type] => utility [patent_app_number] => 17/406224 [patent_app_country] => US [patent_app_date] => 2021-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 30 [patent_no_of_words] => 16622 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17406224 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/406224
Controlling bit line pre-charge voltage separately for multi-level memory cells and single-level memory cells to reduce peak current consumption Aug 18, 2021 Issued
Array ( [id] => 18387095 [patent_doc_number] => 11657884 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-23 [patent_title] => Non-volatile memory with efficient testing during erase [patent_app_type] => utility [patent_app_number] => 17/403052 [patent_app_country] => US [patent_app_date] => 2021-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 25 [patent_no_of_words] => 21291 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17403052 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/403052
Non-volatile memory with efficient testing during erase Aug 15, 2021 Issued
Array ( [id] => 18645482 [patent_doc_number] => 11769560 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-26 [patent_title] => String based erase inhibit [patent_app_type] => utility [patent_app_number] => 17/401749 [patent_app_country] => US [patent_app_date] => 2021-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 30 [patent_no_of_words] => 14622 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17401749 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/401749
String based erase inhibit Aug 12, 2021 Issued
Array ( [id] => 17645055 [patent_doc_number] => 20220172794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => METHOD OF WRITING DATA IN NONVOLATILE MEMORY DEVICE, NONVOLATILE MEMORY DEVICE PERFORMING THE SAME AND METHOD OF OPERATING MEMORY SYSTEM USING THE SAME [patent_app_type] => utility [patent_app_number] => 17/393797 [patent_app_country] => US [patent_app_date] => 2021-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14637 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17393797 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/393797
Method of writing data in nonvolatile memory device, nonvolatile memory device performing the same and method of operating memory system using the same Aug 3, 2021 Issued
Array ( [id] => 18169879 [patent_doc_number] => 20230036490 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => READ THRESHOLD VOLTAGE ESTIMATION SYSTEMS AND METHODS FOR PARAMETRIC PV-LEVEL MODELING [patent_app_type] => utility [patent_app_number] => 17/443726 [patent_app_country] => US [patent_app_date] => 2021-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11667 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17443726 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/443726
Read threshold voltage estimation systems and methods for parametric PV-level modeling Jul 26, 2021 Issued
Array ( [id] => 18149761 [patent_doc_number] => 20230023618 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => ISOLATING PROBLEMATIC MEMORY PLANES TO AVOID NEIGHBOR PLAN DISTURB [patent_app_type] => utility [patent_app_number] => 17/382424 [patent_app_country] => US [patent_app_date] => 2021-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19185 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17382424 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/382424
Isolating problematic memory planes to avoid neighbor plan disturb Jul 21, 2021 Issued
Array ( [id] => 17583122 [patent_doc_number] => 20220139977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => STREAKING-FREE CMOS IMAGE SENSOR WITH ON-GATE DUAL-ELECTRODE PASS TRANSISTOR [patent_app_type] => utility [patent_app_number] => 17/338652 [patent_app_country] => US [patent_app_date] => 2021-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2269 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17338652 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/338652
STREAKING-FREE CMOS IMAGE SENSOR WITH ON-GATE DUAL-ELECTRODE PASS TRANSISTOR Jun 2, 2021 Abandoned
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