
Kretelia Graham
Examiner (ID: 7064)
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2825, 2615, 2817, 2827 |
| Total Applications | 682 |
| Issued Applications | 565 |
| Pending Applications | 4 |
| Abandoned Applications | 116 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 405548
[patent_doc_number] => 07289383
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-10-30
[patent_title] => 'Reducing the number of power and ground pins required to drive address signals to memory modules'
[patent_app_type] => utility
[patent_app_number] => 10/925174
[patent_app_country] => US
[patent_app_date] => 2004-08-23
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/289/07289383.pdf
[firstpage_image] =>[orig_patent_app_number] => 10925174
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/925174 | Reducing the number of power and ground pins required to drive address signals to memory modules | Aug 22, 2004 | Issued |
Array
(
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[patent_doc_number] => 20050002215
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-06
[patent_title] => 'Multiport semiconductor memory device capable of sufficiently steadily holding data and providing a sufficient write margin'
[patent_app_type] => utility
[patent_app_number] => 10/880530
[patent_app_country] => US
[patent_app_date] => 2004-07-01
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Array
(
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[patent_doc_number] => 20050138269
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[patent_issue_date] => 2005-06-23
[patent_title] => 'Memory apparatus having multi-port architecture for supporting multi processor'
[patent_app_type] => utility
[patent_app_number] => 10/879274
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Array
(
[id] => 7172288
[patent_doc_number] => 20050122762
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-09
[patent_title] => 'FeRAM having differential data'
[patent_app_type] => utility
[patent_app_number] => 10/879138
[patent_app_country] => US
[patent_app_date] => 2004-06-30
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/879138 | FeRAM having differential data | Jun 29, 2004 | Issued |
Array
(
[id] => 7141712
[patent_doc_number] => 20050117380
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-02
[patent_title] => 'FeRAM having single ended sensing architecture'
[patent_app_type] => utility
[patent_app_number] => 10/879188
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/879188 | FeRAM having single ended sensing architecture | Jun 29, 2004 | Issued |
Array
(
[id] => 503391
[patent_doc_number] => 07209398
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[patent_issue_date] => 2007-04-24
[patent_title] => 'Semiconductor memory device having redundancy cell array shared by a plurality of memory cell arrays'
[patent_app_type] => utility
[patent_app_number] => 10/879100
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[firstpage_image] =>[orig_patent_app_number] => 10879100
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/879100 | Semiconductor memory device having redundancy cell array shared by a plurality of memory cell arrays | Jun 29, 2004 | Issued |
Array
(
[id] => 5792375
[patent_doc_number] => 20060013056
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[patent_issue_date] => 2006-01-19
[patent_title] => 'Memory architecture'
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[pdf_file] => publications/A1/0013/20060013056.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/879158 | Memory architecture | Jun 29, 2004 | Issued |
Array
(
[id] => 6965170
[patent_doc_number] => 20050232067
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[patent_issue_date] => 2005-10-20
[patent_title] => 'Semiconductor integrated circuit device and data write method thereof'
[patent_app_type] => utility
[patent_app_number] => 10/879297
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/879297 | Semiconductor integrated circuit device and data write method thereof | Jun 29, 2004 | Issued |
Array
(
[id] => 6943616
[patent_doc_number] => 20050195665
[patent_country] => US
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[patent_issue_date] => 2005-09-08
[patent_title] => 'Device information writing circuit'
[patent_app_type] => utility
[patent_app_number] => 10/879130
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/879130 | Device information writing circuit | Jun 29, 2004 | Issued |
Array
(
[id] => 7096333
[patent_doc_number] => 20050128791
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[patent_issue_date] => 2005-06-16
[patent_title] => 'Phase change resistor cell and nonvolatile memory device using the same'
[patent_app_type] => utility
[patent_app_number] => 10/879140
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[pdf_file] => publications/A1/0128/20050128791.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/879140 | Phase change resistor cell and nonvolatile memory device using the same | Jun 29, 2004 | Issued |
Array
(
[id] => 814999
[patent_doc_number] => 07414876
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[patent_issue_date] => 2008-08-19
[patent_title] => 'Nonvolatile ferroelectric memory device having power control function'
[patent_app_type] => utility
[patent_app_number] => 10/879186
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[pdf_file] => patents/07/414/07414876.pdf
[firstpage_image] =>[orig_patent_app_number] => 10879186
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/879186 | Nonvolatile ferroelectric memory device having power control function | Jun 29, 2004 | Issued |
Array
(
[id] => 704714
[patent_doc_number] => 07064989
[patent_country] => US
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[patent_issue_date] => 2006-06-20
[patent_title] => 'On-die termination control circuit and method of generating on-die termination control signal'
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[patent_app_number] => 10/879386
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/879386 | On-die termination control circuit and method of generating on-die termination control signal | Jun 28, 2004 | Issued |
Array
(
[id] => 545307
[patent_doc_number] => 07173866
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[patent_issue_date] => 2007-02-06
[patent_title] => 'Circuit for generating data strobe signal in DDR memory device, and method therefor'
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[patent_app_number] => 10/879878
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/879878 | Circuit for generating data strobe signal in DDR memory device, and method therefor | Jun 28, 2004 | Issued |
Array
(
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Array
(
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Array
(
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Array
(
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Array
(
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/520340 | Erasable and programmable non-volatile cell | Jun 24, 2003 | Issued |