Search

Kretelia Graham

Examiner (ID: 11675, Phone: (571)272-5055 , Office: P/2825 )

Most Active Art Unit
2827
Art Unit(s)
2817, 2827, 2615, 2825
Total Applications
682
Issued Applications
562
Pending Applications
12
Abandoned Applications
115

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10270038 [patent_doc_number] => 20150155035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-04 [patent_title] => 'RESISTANCE-CHANGE MEMORY' [patent_app_type] => utility [patent_app_number] => 14/621071 [patent_app_country] => US [patent_app_date] => 2015-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 6251 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14621071 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/621071
Resistance-change memory having on-state, off-state, and intermediate state Feb 11, 2015 Issued
Array ( [id] => 10336381 [patent_doc_number] => 20150221386 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-06 [patent_title] => 'METHOD AND DEVICE FOR TEMPERATURE-BASED DATA REFRESH IN NON-VOLATILE MEMORIES' [patent_app_type] => utility [patent_app_number] => 14/617674 [patent_app_country] => US [patent_app_date] => 2015-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8319 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14617674 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/617674
Method and device for temperature-based data refresh in non-volatile memories Feb 8, 2015 Issued
Array ( [id] => 10264741 [patent_doc_number] => 20150149738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-28 [patent_title] => 'CONTINUOUS PAGE READ FOR MEMORY' [patent_app_type] => utility [patent_app_number] => 14/610977 [patent_app_country] => US [patent_app_date] => 2015-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7234 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14610977 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/610977
Continuous page read for memory Jan 29, 2015 Issued
Array ( [id] => 11637651 [patent_doc_number] => 09659631 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-23 [patent_title] => 'Current sense amplifiers, memory devices and methods' [patent_app_type] => utility [patent_app_number] => 14/602084 [patent_app_country] => US [patent_app_date] => 2015-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3075 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14602084 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/602084
Current sense amplifiers, memory devices and methods Jan 20, 2015 Issued
Array ( [id] => 10283501 [patent_doc_number] => 20150168499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-18 [patent_title] => 'BATTERY TESTER AND BATTERY REGISTRATION TOOL' [patent_app_type] => utility [patent_app_number] => 14/565589 [patent_app_country] => US [patent_app_date] => 2014-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5974 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14565589 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/565589
BATTERY TESTER AND BATTERY REGISTRATION TOOL Dec 9, 2014 Abandoned
Array ( [id] => 10825876 [patent_doc_number] => 20160172044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'Method To Recover Cycling Damage And Improve Long Term Data Retention' [patent_app_type] => utility [patent_app_number] => 14/565729 [patent_app_country] => US [patent_app_date] => 2014-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 17093 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14565729 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/565729
Method to recover cycling damage and improve long term data retention Dec 9, 2014 Issued
Array ( [id] => 10638218 [patent_doc_number] => 09355727 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-05-31 [patent_title] => 'Three-dimensional memory structure having a back gate electrode' [patent_app_type] => utility [patent_app_number] => 14/564555 [patent_app_country] => US [patent_app_date] => 2014-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 55 [patent_no_of_words] => 29328 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14564555 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/564555
Three-dimensional memory structure having a back gate electrode Dec 8, 2014 Issued
Array ( [id] => 11585621 [patent_doc_number] => 09640271 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-02 [patent_title] => 'Low-dropout regulator peak current control' [patent_app_type] => utility [patent_app_number] => 14/564821 [patent_app_country] => US [patent_app_date] => 2014-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5599 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14564821 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/564821
Low-dropout regulator peak current control Dec 8, 2014 Issued
Array ( [id] => 10531038 [patent_doc_number] => 09257178 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-02-09 [patent_title] => 'Devices and methods for writing to a memory cell of a memory' [patent_app_type] => utility [patent_app_number] => 14/554547 [patent_app_country] => US [patent_app_date] => 2014-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5703 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14554547 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/554547
Devices and methods for writing to a memory cell of a memory Nov 25, 2014 Issued
Array ( [id] => 11346093 [patent_doc_number] => 09530506 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-27 [patent_title] => 'NAND boosting using dynamic ramping of word line voltages' [patent_app_type] => utility [patent_app_number] => 14/550897 [patent_app_country] => US [patent_app_date] => 2014-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 28 [patent_no_of_words] => 15486 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14550897 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/550897
NAND boosting using dynamic ramping of word line voltages Nov 20, 2014 Issued
Array ( [id] => 10794875 [patent_doc_number] => 20160141032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-19 [patent_title] => 'EEPROM ARCHITECTURE WHEREIN EACH BIT IS FORMED BY TWO SERIALLY CONNECTED CELLS' [patent_app_type] => utility [patent_app_number] => 14/547199 [patent_app_country] => US [patent_app_date] => 2014-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4207 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14547199 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/547199
EEPROM architecture wherein each bit is formed by two serially connected cells Nov 18, 2014 Issued
Array ( [id] => 10518592 [patent_doc_number] => 09245646 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-26 [patent_title] => 'Program verify operation in a memory device' [patent_app_type] => utility [patent_app_number] => 14/528251 [patent_app_country] => US [patent_app_date] => 2014-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2878 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14528251 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/528251
Program verify operation in a memory device Oct 29, 2014 Issued
Array ( [id] => 10659611 [patent_doc_number] => 20160005755 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-07 [patent_title] => 'NON-VOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/521577 [patent_app_country] => US [patent_app_date] => 2014-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9287 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14521577 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/521577
Memory device with different memory film diameters in the same laminate level Oct 22, 2014 Issued
Array ( [id] => 9841014 [patent_doc_number] => 20150033096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-29 [patent_title] => 'MEMORY DEVICES AND CONFIGURATION METHODS FOR A MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/513880 [patent_app_country] => US [patent_app_date] => 2014-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6953 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14513880 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/513880
Configuring and reconfiguring blocks of memory cells to store user data and ECC data Oct 13, 2014 Issued
Array ( [id] => 10745965 [patent_doc_number] => 20160092116 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'MULTI-TIER SCHEME FOR LOGICAL STORAGE MANAGEMENT' [patent_app_type] => utility [patent_app_number] => 14/498566 [patent_app_country] => US [patent_app_date] => 2014-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11093 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14498566 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/498566
Multi-tier scheme for logical storage management Sep 25, 2014 Issued
Array ( [id] => 10732795 [patent_doc_number] => 20160078945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-17 [patent_title] => 'INCREMENTAL STEP PULSE PROGRAMMING' [patent_app_type] => utility [patent_app_number] => 14/487769 [patent_app_country] => US [patent_app_date] => 2014-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4263 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14487769 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/487769
Incremental step pulse programming Sep 15, 2014 Issued
Array ( [id] => 9856406 [patent_doc_number] => 20150036423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-05 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/457398 [patent_app_country] => US [patent_app_date] => 2014-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 9792 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14457398 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/457398
Semiconductor device with low voltage programming/erasing operations Aug 11, 2014 Issued
Array ( [id] => 10207493 [patent_doc_number] => 20150092481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-02 [patent_title] => 'ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/444969 [patent_app_country] => US [patent_app_date] => 2014-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12312 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14444969 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/444969
Electronic device having a variable resistance element with a protection layer and method for fabricating the same Jul 27, 2014 Issued
Array ( [id] => 10336380 [patent_doc_number] => 20150221385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-06 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND SYSTEM INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/333243 [patent_app_country] => US [patent_app_date] => 2014-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9773 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14333243 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/333243
SEMICONDUCTOR MEMORY DEVICE AND SYSTEM INCLUDING THE SAME Jul 15, 2014 Abandoned
Array ( [id] => 10918203 [patent_doc_number] => 20140321222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-30 [patent_title] => 'SEMICONDUCTOR MEMORY OF WHICH DEFECTIVE CELL IS REPLACEABLE WITH REDUNDANT CELL AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY' [patent_app_type] => utility [patent_app_number] => 14/331401 [patent_app_country] => US [patent_app_date] => 2014-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 12398 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14331401 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/331401
Semiconductor memory of which defective cell is replaceable with redundant cell and manufacturing method of semiconductor memory Jul 14, 2014 Issued
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