
Kriellion Antionette Sanders
Examiner (ID: 8649)
| Most Active Art Unit | 1714 |
| Art Unit(s) | 1761, 1768, 1503, 1511, 1714, 1796, 1509 |
| Total Applications | 2736 |
| Issued Applications | 2061 |
| Pending Applications | 79 |
| Abandoned Applications | 597 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 191245
[patent_doc_number] => 07642557
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-01-05
[patent_title] => 'Non-contact pumping of light emitters via non-radiative energy transfer'
[patent_app_type] => utility
[patent_app_number] => 10/843737
[patent_app_country] => US
[patent_app_date] => 2004-05-11
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/642/07642557.pdf
[firstpage_image] =>[orig_patent_app_number] => 10843737
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/843737 | Non-contact pumping of light emitters via non-radiative energy transfer | May 10, 2004 | Issued |
Array
(
[id] => 281701
[patent_doc_number] => 07553700
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-06-30
[patent_title] => 'Chemical-enhanced package singulation process'
[patent_app_type] => utility
[patent_app_number] => 10/843867
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/843867 | Chemical-enhanced package singulation process | May 10, 2004 | Issued |
Array
(
[id] => 513260
[patent_doc_number] => 07196401
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[patent_kind] => B2
[patent_issue_date] => 2007-03-27
[patent_title] => 'Chip-packaging with bonding options having a plurality of package substrates'
[patent_app_type] => utility
[patent_app_number] => 10/709427
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[patent_app_date] => 2004-05-05
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/709427 | Chip-packaging with bonding options having a plurality of package substrates | May 4, 2004 | Issued |
Array
(
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[patent_doc_number] => 20040262704
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[patent_issue_date] => 2004-12-30
[patent_title] => 'Semiconductor package with an optical sensor which may be fit inside an object'
[patent_app_type] => new
[patent_app_number] => 10/825077
[patent_app_country] => US
[patent_app_date] => 2004-04-15
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[firstpage_image] =>[orig_patent_app_number] => 10825077
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/825077 | Semiconductor package with an optical sensor which may be fit inside an object | Apr 14, 2004 | Issued |
Array
(
[id] => 638251
[patent_doc_number] => 07126168
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[patent_issue_date] => 2006-10-24
[patent_title] => 'Silicon controlled rectifier structures with reduced turn on times'
[patent_app_type] => utility
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[pdf_file] => patents/07/126/07126168.pdf
[firstpage_image] =>[orig_patent_app_number] => 10821287
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/821287 | Silicon controlled rectifier structures with reduced turn on times | Apr 8, 2004 | Issued |
Array
(
[id] => 6949749
[patent_doc_number] => 20050224843
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[patent_issue_date] => 2005-10-13
[patent_title] => 'High dynamic range pixel amplifier'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/819167 | High dynamic range pixel amplifier | Apr 6, 2004 | Issued |
Array
(
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[patent_title] => 'Method for fabricating a semiconductor structure using a protective layer, and semiconductor structure'
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[patent_app_date] => 2004-04-01
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/815407 | Method for fabricating a semiconductor structure using a protective layer, and semiconductor structure | Mar 31, 2004 | Issued |
Array
(
[id] => 7609505
[patent_doc_number] => 06998684
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[patent_issue_date] => 2006-02-14
[patent_title] => 'High mobility plane CMOS SOI'
[patent_app_type] => utility
[patent_app_number] => 10/708907
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[pdf_file] => patents/06/998/06998684.pdf
[firstpage_image] =>[orig_patent_app_number] => 10708907
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/708907 | High mobility plane CMOS SOI | Mar 30, 2004 | Issued |
Array
(
[id] => 751736
[patent_doc_number] => 07023037
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[patent_kind] => B2
[patent_issue_date] => 2006-04-04
[patent_title] => 'Integrated circuit devices having dielectric regions protected with multi-layer insulation structures'
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[patent_app_number] => 10/813335
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/813335 | Integrated circuit devices having dielectric regions protected with multi-layer insulation structures | Mar 29, 2004 | Issued |
Array
(
[id] => 7036767
[patent_doc_number] => 20050156201
[patent_country] => US
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[patent_issue_date] => 2005-07-21
[patent_title] => 'Semiconductor device'
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[patent_app_number] => 10/807247
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/807247 | Semiconductor device | Mar 23, 2004 | Issued |
Array
(
[id] => 6955688
[patent_doc_number] => 20050212058
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[patent_title] => 'Resistance-reduced semiconductor device and fabrication thereof'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/806217 | Resistance-reduced semiconductor device and fabrication thereof | Mar 22, 2004 | Abandoned |
Array
(
[id] => 691955
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[patent_title] => 'Power semiconductor device'
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Array
(
[id] => 7016458
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[patent_title] => 'Low power fuse structure and method for making the same'
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Array
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Array
(
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[patent_title] => 'Embedded semiconductor product with dual depth isolation regions'
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Array
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