Search

Kriellion Antionette Sanders

Examiner (ID: 8649)

Most Active Art Unit
1714
Art Unit(s)
1761, 1768, 1503, 1511, 1714, 1796, 1509
Total Applications
2736
Issued Applications
2061
Pending Applications
79
Abandoned Applications
597

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7072666 [patent_doc_number] => 20050145932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-07 [patent_title] => 'Vertical channel field effect transistors having insulating layers thereon and methods of fabricating the same' [patent_app_type] => utility [patent_app_number] => 10/780067 [patent_app_country] => US [patent_app_date] => 2004-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 6198 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20050145932.pdf [firstpage_image] =>[orig_patent_app_number] => 10780067 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/780067
Vertical channel field effect transistors having insulating layers thereon Feb 16, 2004 Issued
Array ( [id] => 502816 [patent_doc_number] => 07205573 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-17 [patent_title] => 'Light-emitting device having a compound substrate' [patent_app_type] => utility [patent_app_number] => 10/708047 [patent_app_country] => US [patent_app_date] => 2004-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1740 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/205/07205573.pdf [firstpage_image] =>[orig_patent_app_number] => 10708047 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/708047
Light-emitting device having a compound substrate Feb 4, 2004 Issued
Array ( [id] => 623982 [patent_doc_number] => 07138691 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-21 [patent_title] => 'Selective nitridation of gate oxides' [patent_app_type] => utility [patent_app_number] => 10/707897 [patent_app_country] => US [patent_app_date] => 2004-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4603 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/138/07138691.pdf [firstpage_image] =>[orig_patent_app_number] => 10707897 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/707897
Selective nitridation of gate oxides Jan 21, 2004 Issued
Array ( [id] => 7677561 [patent_doc_number] => 20040152265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'Method for forming MRAM bit having a bottom sense layer utilizing electroless plating' [patent_app_type] => new [patent_app_number] => 10/761247 [patent_app_country] => US [patent_app_date] => 2004-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4242 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0152/20040152265.pdf [firstpage_image] =>[orig_patent_app_number] => 10761247 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/761247
MRAM memory cell having an electroplated bottom layer Jan 21, 2004 Issued
Array ( [id] => 975954 [patent_doc_number] => 06933571 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-23 [patent_title] => 'Thin film transistors, liquid crystal display device and electronic apparatus using the same' [patent_app_type] => utility [patent_app_number] => 10/757452 [patent_app_country] => US [patent_app_date] => 2004-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 9035 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/933/06933571.pdf [firstpage_image] =>[orig_patent_app_number] => 10757452 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/757452
Thin film transistors, liquid crystal display device and electronic apparatus using the same Jan 14, 2004 Issued
Array ( [id] => 6983404 [patent_doc_number] => 20050153474 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-14 [patent_title] => 'Vertical optical path structure for infrared photodetection' [patent_app_type] => utility [patent_app_number] => 10/755567 [patent_app_country] => US [patent_app_date] => 2004-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4097 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20050153474.pdf [firstpage_image] =>[orig_patent_app_number] => 10755567 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/755567
Vertical optical path structure for infrared photodetection Jan 11, 2004 Issued
Array ( [id] => 7309406 [patent_doc_number] => 20040142582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-22 [patent_title] => 'Thin film structure from LILAC annealing' [patent_app_type] => new [patent_app_number] => 10/755487 [patent_app_country] => US [patent_app_date] => 2004-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4022 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20040142582.pdf [firstpage_image] =>[orig_patent_app_number] => 10755487 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/755487
Thin film structure from LILAC annealing Jan 11, 2004 Issued
Array ( [id] => 7304861 [patent_doc_number] => 20040140496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-22 [patent_title] => 'Bitline structure for DRAM and method of forming the same' [patent_app_type] => new [patent_app_number] => 10/752961 [patent_app_country] => US [patent_app_date] => 2004-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2238 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20040140496.pdf [firstpage_image] =>[orig_patent_app_number] => 10752961 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/752961
Bitline structure for DRAM and method of forming the same Jan 6, 2004 Issued
Array ( [id] => 7260129 [patent_doc_number] => 20040150038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'Trench MOSFET having low gate charge' [patent_app_type] => new [patent_app_number] => 10/751687 [patent_app_country] => US [patent_app_date] => 2004-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 6274 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20040150038.pdf [firstpage_image] =>[orig_patent_app_number] => 10751687 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/751687
Trench MOSFET having low gate charge Jan 4, 2004 Issued
Array ( [id] => 7304871 [patent_doc_number] => 20040140506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-22 [patent_title] => 'Enhanced T-gate structure for modulation doped field effect transistors' [patent_app_type] => new [patent_app_number] => 10/750697 [patent_app_country] => US [patent_app_date] => 2004-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4139 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20040140506.pdf [firstpage_image] =>[orig_patent_app_number] => 10750697 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/750697
Enhanced T-gate structure for modulation doped field effect transistors Jan 1, 2004 Issued
Array ( [id] => 673008 [patent_doc_number] => 07091570 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-15 [patent_title] => 'MOS device and a process for manufacturing MOS devices using a dual-polysilicon layer technology with side contact' [patent_app_type] => utility [patent_app_number] => 10/745297 [patent_app_country] => US [patent_app_date] => 2003-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2812 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/091/07091570.pdf [firstpage_image] =>[orig_patent_app_number] => 10745297 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/745297
MOS device and a process for manufacturing MOS devices using a dual-polysilicon layer technology with side contact Dec 22, 2003 Issued
Array ( [id] => 6970672 [patent_doc_number] => 20050036382 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-17 [patent_title] => 'Semiconductor memory element, semiconductor memory device and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 10/735717 [patent_app_country] => US [patent_app_date] => 2003-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 13645 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20050036382.pdf [firstpage_image] =>[orig_patent_app_number] => 10735717 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/735717
Semiconductor memory element, semiconductor memory device and method of fabricating the same Dec 15, 2003 Issued
Array ( [id] => 5820578 [patent_doc_number] => 20060024891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-02 [patent_title] => 'Method of manufacture of a trench-gate semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/538217 [patent_app_country] => US [patent_app_date] => 2003-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2420 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20060024891.pdf [firstpage_image] =>[orig_patent_app_number] => 10538217 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/538217
Method of manufacture of a trench-gate semiconductor device Dec 7, 2003 Issued
Array ( [id] => 7626598 [patent_doc_number] => 06768164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-27 [patent_title] => 'Stacked gate flash memory device and method of fabricating the same' [patent_app_type] => B2 [patent_app_number] => 10/725052 [patent_app_country] => US [patent_app_date] => 2003-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 3319 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 8 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/768/06768164.pdf [firstpage_image] =>[orig_patent_app_number] => 10725052 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/725052
Stacked gate flash memory device and method of fabricating the same Nov 30, 2003 Issued
Array ( [id] => 7198671 [patent_doc_number] => 20050051861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-10 [patent_title] => 'Avalanche photo-detector with high saturation power and high gain-bandwidth product' [patent_app_type] => utility [patent_app_number] => 10/720117 [patent_app_country] => US [patent_app_date] => 2003-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3653 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20050051861.pdf [firstpage_image] =>[orig_patent_app_number] => 10720117 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/720117
Avalanche photo-detector with high saturation power and high gain-bandwidth product Nov 24, 2003 Issued
Array ( [id] => 6936497 [patent_doc_number] => 20050110058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-26 [patent_title] => 'Method and structure for reducing resistance of a semiconductor device feature' [patent_app_type] => utility [patent_app_number] => 10/719047 [patent_app_country] => US [patent_app_date] => 2003-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3264 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20050110058.pdf [firstpage_image] =>[orig_patent_app_number] => 10719047 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/719047
Method and structure for reducing resistance of a semiconductor device feature Nov 19, 2003 Issued
Array ( [id] => 7101347 [patent_doc_number] => 20050104073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-19 [patent_title] => 'Solid-state display with improved color-mixing' [patent_app_type] => utility [patent_app_number] => 10/715927 [patent_app_country] => US [patent_app_date] => 2003-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 1993 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20050104073.pdf [firstpage_image] =>[orig_patent_app_number] => 10715927 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/715927
Solid-state display with improved color-mixing Nov 17, 2003 Issued
Array ( [id] => 751895 [patent_doc_number] => 07023068 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-04 [patent_title] => 'Method of etching a lateral trench under a drain junction of a MOS transistor' [patent_app_type] => utility [patent_app_number] => 10/716277 [patent_app_country] => US [patent_app_date] => 2003-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 16 [patent_no_of_words] => 1913 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/023/07023068.pdf [firstpage_image] =>[orig_patent_app_number] => 10716277 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/716277
Method of etching a lateral trench under a drain junction of a MOS transistor Nov 16, 2003 Issued
Array ( [id] => 7399923 [patent_doc_number] => 20040105023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-03 [patent_title] => 'Solid state imaging device with an output section having reduced power consumption, and manufacturing method thereof' [patent_app_type] => new [patent_app_number] => 10/713487 [patent_app_country] => US [patent_app_date] => 2003-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4785 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20040105023.pdf [firstpage_image] =>[orig_patent_app_number] => 10713487 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/713487
Solid state imaging device with an output section having reduced power consumption, and manufacturing method thereof Nov 13, 2003 Abandoned
Array ( [id] => 1044095 [patent_doc_number] => 06867460 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-15 [patent_title] => 'FinFET SRAM cell with chevron FinFET logic' [patent_app_type] => utility [patent_app_number] => 10/605907 [patent_app_country] => US [patent_app_date] => 2003-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 6112 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/867/06867460.pdf [firstpage_image] =>[orig_patent_app_number] => 10605907 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/605907
FinFET SRAM cell with chevron FinFET logic Nov 4, 2003 Issued
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