Kriellion Antionette Sanders

Array ( [id] => 5981954 [patent_doc_number] => 20020096716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-25 [patent_title] => 'Structure and method of MOS transistor having increased substrate resistance' [patent_app_type] => new [patent_app_number] => 10/043507 [patent_app_country] => US [patent_app_date] => 2002-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5283 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20020096716.pdf [firstpage_image] =>[orig_patent_app_number] => 10043507 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1386624 [patent_doc_number] => 06555879 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-29 [patent_title] => 'SOI device with metal source/drain and method of fabrication' [patent_app_type] => B1 [patent_app_number] => 10/044247 [patent_app_country] => US [patent_app_date] => 2002-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4804 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/555/06555879.pdf [firstpage_image] =>[orig_patent_app_number] => 10044247 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1379928 [patent_doc_number] => 06563176 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-13 [patent_title] => 'Asymmetrical semiconductor device for ESD protection' [patent_app_type] => B2 [patent_app_number] => 10/041509 [patent_app_country] => US [patent_app_date] => 2002-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3280 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/563/06563176.pdf [firstpage_image] =>[orig_patent_app_number] => 10041509 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1158257 [patent_doc_number] => 06765236 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-20 [patent_title] => 'Optical device and method for manufacturing the same, and electronic apparatus' [patent_app_type] => B2 [patent_app_number] => 10/032227 [patent_app_country] => US [patent_app_date] => 2001-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4130 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/765/06765236.pdf [firstpage_image] =>[orig_patent_app_number] => 10032227 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1364732 [patent_doc_number] => 06573589 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-03 [patent_title] => 'Semiconductor device and process for fabricating the same' [patent_app_type] => B2 [patent_app_number] => 10/022250 [patent_app_country] => US [patent_app_date] => 2001-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 3662 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/573/06573589.pdf [firstpage_image] =>[orig_patent_app_number] => 10022250 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1254216 [patent_doc_number] => 06670649 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-30 [patent_title] => 'Triodic rectifier switch' [patent_app_type] => B2 [patent_app_number] => 10/012397 [patent_app_country] => US [patent_app_date] => 2001-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 3994 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/670/06670649.pdf [firstpage_image] =>[orig_patent_app_number] => 10012397 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6284905 [patent_doc_number] => 20020053681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-09 [patent_title] => 'Semiconductor light emitting element' [patent_app_type] => new [patent_app_number] => 10/012106 [patent_app_country] => US [patent_app_date] => 2001-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5358 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20020053681.pdf [firstpage_image] =>[orig_patent_app_number] => 10012106 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 757660 [patent_doc_number] => 07015105 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-21 [patent_title] => 'Method of simultaneously making a pair of transistors with insulated gates having respectively a thin oxide and a thick oxide, and corresponding integrated circuit comprising such a pair of transistors' [patent_app_type] => utility [patent_app_number] => 10/169237 [patent_app_country] => US [patent_app_date] => 2001-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 2529 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/015/07015105.pdf [firstpage_image] =>[orig_patent_app_number] => 10169237 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6076086 [patent_doc_number] => 20020079587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-27 [patent_title] => 'Method and apparatus for reducing capacitive coupling between lines in an integrated circuit' [patent_app_type] => new [patent_app_number] => 10/001707 [patent_app_country] => US [patent_app_date] => 2001-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4575 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20020079587.pdf [firstpage_image] =>[orig_patent_app_number] => 10001707 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6933376 [patent_doc_number] => 20010054720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-27 [patent_title] => 'Power/ground metallization routing in a semiconductor device' [patent_app_type] => new [patent_app_number] => 09/929320 [patent_app_country] => US [patent_app_date] => 2001-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3005 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20010054720.pdf [firstpage_image] =>[orig_patent_app_number] => 09929320 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1368578 [patent_doc_number] => 06570224 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Quantum-size electronic devices and operating conditions thereof' [patent_app_type] => B1 [patent_app_number] => 09/622067 [patent_app_country] => US [patent_app_date] => 2001-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 39 [patent_no_of_words] => 25813 [patent_no_of_claims] => 102 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/570/06570224.pdf [firstpage_image] =>[orig_patent_app_number] => 09622067 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1330600 [patent_doc_number] => 06600204 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-29 [patent_title] => 'Low-voltage punch-through bi-directional transient-voltage suppression devices having surface breakdown protection and methods of making the same' [patent_app_type] => B2 [patent_app_number] => 09/903107 [patent_app_country] => US [patent_app_date] => 2001-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6472 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/600/06600204.pdf [firstpage_image] =>[orig_patent_app_number] => 09903107 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1074108 [patent_doc_number] => 06838773 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-04 [patent_title] => 'Semiconductor chip and semiconductor device using the semiconductor chip' [patent_app_type] => utility [patent_app_number] => 10/311707 [patent_app_country] => US [patent_app_date] => 2001-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 29 [patent_no_of_words] => 10513 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/838/06838773.pdf [firstpage_image] =>[orig_patent_app_number] => 10311707 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1069257 [patent_doc_number] => 06844625 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-18 [patent_title] => 'Method for producing input/output permutation of several conductive strips with parallel branches of an integrated circuit and resulting circuit' [patent_app_type] => utility [patent_app_number] => 10/297467 [patent_app_country] => US [patent_app_date] => 2001-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 6160 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 392 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/844/06844625.pdf [firstpage_image] =>[orig_patent_app_number] => 10297467 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1428393 [patent_doc_number] => 06504235 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-07 [patent_title] => 'Passivation layer and process for semiconductor devices' [patent_app_type] => B2 [patent_app_number] => 09/876538 [patent_app_country] => US [patent_app_date] => 2001-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4722 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/504/06504235.pdf [firstpage_image] =>[orig_patent_app_number] => 09876538 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6426021 [patent_doc_number] => 20020184558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'SUBSTRATE NOISE ISOLATION USING SELECTIVE BURIED DIFFUSIONS' [patent_app_type] => new [patent_app_number] => 09/871407 [patent_app_country] => US [patent_app_date] => 2001-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2705 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20020184558.pdf [firstpage_image] =>[orig_patent_app_number] => 09871407 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6920594 [patent_doc_number] => 20010028079 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-11 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 09/866662 [patent_app_country] => US [patent_app_date] => 2001-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 51 [patent_no_of_words] => 13412 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20010028079.pdf [firstpage_image] =>[orig_patent_app_number] => 09866662 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1225046 [patent_doc_number] => 06700134 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-02 [patent_title] => 'Semiconductor device provided with semiconductor circuit consisting of semiconductor element and method of manufacturing the same' [patent_app_type] => B2 [patent_app_number] => 09/852160 [patent_app_country] => US [patent_app_date] => 2001-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 39 [patent_no_of_words] => 14968 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/700/06700134.pdf [firstpage_image] =>[orig_patent_app_number] => 09852160 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1178280 [patent_doc_number] => 06747289 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-08 [patent_title] => 'Semiconductor device and method of fabricating thereof' [patent_app_type] => B2 [patent_app_number] => 09/841537 [patent_app_country] => US [patent_app_date] => 2001-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 70 [patent_no_of_words] => 18008 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/747/06747289.pdf [firstpage_image] =>[orig_patent_app_number] => 09841537 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1360257 [patent_doc_number] => 06576958 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-10 [patent_title] => 'ESD protection networks with NMOS-bound or PMOS-bound diode structures in a shallow-trench-isolation (STI) CMOS process' [patent_app_type] => B2 [patent_app_number] => 09/836217 [patent_app_country] => US [patent_app_date] => 2001-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 38 [patent_no_of_words] => 5982 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/576/06576958.pdf [firstpage_image] =>[orig_patent_app_number] => 09836217 [rel_patent_id] =>[rel_patent_doc_number] =>)