
Kriellion Antionette Sanders
Examiner (ID: 8649)
| Most Active Art Unit | 1714 |
| Art Unit(s) | 1761, 1768, 1503, 1511, 1714, 1796, 1509 |
| Total Applications | 2736 |
| Issued Applications | 2061 |
| Pending Applications | 79 |
| Abandoned Applications | 597 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1440951
[patent_doc_number] => 06495857
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-12-17
[patent_title] => 'Thin film transister semiconductor devices'
[patent_app_type] => B2
[patent_app_number] => 09/749864
[patent_app_country] => US
[patent_app_date] => 2000-12-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 12
[patent_no_of_words] => 3813
[patent_no_of_claims] => 60
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/495/06495857.pdf
[firstpage_image] =>[orig_patent_app_number] => 09749864
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/749864 | Thin film transister semiconductor devices | Dec 25, 2000 | Issued |
Array
(
[id] => 1314395
[patent_doc_number] => 06614094
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-09-02
[patent_title] => 'High integration density vertical capacitor structure and fabrication process'
[patent_app_type] => B2
[patent_app_number] => 09/747167
[patent_app_country] => US
[patent_app_date] => 2000-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 14
[patent_no_of_words] => 2767
[patent_no_of_claims] => 19
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[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/614/06614094.pdf
[firstpage_image] =>[orig_patent_app_number] => 09747167
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/747167 | High integration density vertical capacitor structure and fabrication process | Dec 20, 2000 | Issued |
Array
(
[id] => 6973632
[patent_doc_number] => 20010003679
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-06-14
[patent_title] => 'Etch stop use in etching of silicon oxide'
[patent_app_type] => new-utility
[patent_app_number] => 09/745848
[patent_app_country] => US
[patent_app_date] => 2000-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3878
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 40
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0003/20010003679.pdf
[firstpage_image] =>[orig_patent_app_number] => 09745848
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/745848 | Etch stop for use in etching of silicon oxide | Dec 20, 2000 | Issued |
Array
(
[id] => 6879056
[patent_doc_number] => 20010030341
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-10-18
[patent_title] => 'Virtual-ground, split-gate flash memory cell arrangements and method for producing same'
[patent_app_type] => new
[patent_app_number] => 09/741667
[patent_app_country] => US
[patent_app_date] => 2000-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4159
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0030/20010030341.pdf
[firstpage_image] =>[orig_patent_app_number] => 09741667
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/741667 | Virtual-ground, split-gate flash memory cell arrangements and method for producing same | Dec 18, 2000 | Issued |
Array
(
[id] => 6123437
[patent_doc_number] => 20020074613
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-06-20
[patent_title] => 'TRENCH SCHOTTKY BARRIER RECTIFIER AND METHOD OF MAKING THE SAME'
[patent_app_type] => new
[patent_app_number] => 09/737357
[patent_app_country] => US
[patent_app_date] => 2000-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 4028
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0074/20020074613.pdf
[firstpage_image] =>[orig_patent_app_number] => 09737357
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/737357 | Trench schottky barrier rectifier and method of making the same | Dec 14, 2000 | Issued |
Array
(
[id] => 1221709
[patent_doc_number] => 06703662
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-03-09
[patent_title] => 'Semiconductor device and manufacturing method thereof'
[patent_app_type] => B1
[patent_app_number] => 09/723387
[patent_app_country] => US
[patent_app_date] => 2000-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 2024
[patent_no_of_claims] => 3
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/703/06703662.pdf
[firstpage_image] =>[orig_patent_app_number] => 09723387
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/723387 | Semiconductor device and manufacturing method thereof | Nov 27, 2000 | Issued |
Array
(
[id] => 1505442
[patent_doc_number] => 06465863
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-10-15
[patent_title] => 'Power diode structure'
[patent_app_type] => B1
[patent_app_number] => 09/701527
[patent_app_country] => US
[patent_app_date] => 2000-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 2811
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 179
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/465/06465863.pdf
[firstpage_image] =>[orig_patent_app_number] => 09701527
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/701527 | Power diode structure | Nov 27, 2000 | Issued |
Array
(
[id] => 1518976
[patent_doc_number] => 06501151
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-31
[patent_title] => 'Integrated capacitor with a mixed dielectric'
[patent_app_type] => B1
[patent_app_number] => 09/714027
[patent_app_country] => US
[patent_app_date] => 2000-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 7
[patent_no_of_words] => 2932
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 58
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/501/06501151.pdf
[firstpage_image] =>[orig_patent_app_number] => 09714027
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/714027 | Integrated capacitor with a mixed dielectric | Nov 14, 2000 | Issued |
Array
(
[id] => 1497007
[patent_doc_number] => 06404014
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-11
[patent_title] => 'Planar and densely patterned silicon-on-insulator structure'
[patent_app_type] => B1
[patent_app_number] => 09/708337
[patent_app_country] => US
[patent_app_date] => 2000-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 3098
[patent_no_of_claims] => 7
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/404/06404014.pdf
[firstpage_image] =>[orig_patent_app_number] => 09708337
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/708337 | Planar and densely patterned silicon-on-insulator structure | Nov 7, 2000 | Issued |
Array
(
[id] => 1536420
[patent_doc_number] => 06489641
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-03
[patent_title] => 'Sea-of-cells array of transistors'
[patent_app_type] => B1
[patent_app_number] => 09/703767
[patent_app_country] => US
[patent_app_date] => 2000-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 18
[patent_no_of_words] => 3745
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/489/06489641.pdf
[firstpage_image] =>[orig_patent_app_number] => 09703767
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/703767 | Sea-of-cells array of transistors | Oct 31, 2000 | Issued |
| 09/697307 | High voltage semiconductor device using sipos and method for fabricating the same | Oct 26, 2000 | Abandoned |
Array
(
[id] => 1580304
[patent_doc_number] => 06448619
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-10
[patent_title] => 'Semiconductor device'
[patent_app_type] => B1
[patent_app_number] => 09/696787
[patent_app_country] => US
[patent_app_date] => 2000-10-26
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/448/06448619.pdf
[firstpage_image] =>[orig_patent_app_number] => 09696787
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/696787 | Semiconductor device | Oct 25, 2000 | Issued |
Array
(
[id] => 1284511
[patent_doc_number] => 06642590
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-11-04
[patent_title] => 'Metal gate with PVD amorphous silicon layer and barrier layer for CMOS devices and method of making with a replacement gate process'
[patent_app_type] => B1
[patent_app_number] => 09/691227
[patent_app_country] => US
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[pdf_file] => patents/06/642/06642590.pdf
[firstpage_image] =>[orig_patent_app_number] => 09691227
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/691227 | Metal gate with PVD amorphous silicon layer and barrier layer for CMOS devices and method of making with a replacement gate process | Oct 18, 2000 | Issued |
Array
(
[id] => 1463705
[patent_doc_number] => 06351023
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-26
[patent_title] => 'Semiconductor device having ultra-sharp P-N junction and method of manufacturing the same'
[patent_app_type] => B1
[patent_app_number] => 09/689660
[patent_app_country] => US
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[pdf_file] => patents/06/351/06351023.pdf
[firstpage_image] =>[orig_patent_app_number] => 09689660
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/689660 | Semiconductor device having ultra-sharp P-N junction and method of manufacturing the same | Oct 12, 2000 | Issued |
Array
(
[id] => 1491861
[patent_doc_number] => 06417560
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-09
[patent_title] => 'Semiconductor device'
[patent_app_type] => B1
[patent_app_number] => 09/679117
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[firstpage_image] =>[orig_patent_app_number] => 09679117
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/679117 | Semiconductor device | Oct 3, 2000 | Issued |
Array
(
[id] => 1529432
[patent_doc_number] => 06479861
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[patent_kind] => B1
[patent_issue_date] => 2002-11-12
[patent_title] => 'Method for forming an etch mask during the manufacture of a semiconductor device'
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[patent_app_number] => 09/677267
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[firstpage_image] =>[orig_patent_app_number] => 09677267
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/677267 | Method for forming an etch mask during the manufacture of a semiconductor device | Sep 25, 2000 | Issued |
Array
(
[id] => 1427951
[patent_doc_number] => 06504187
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-01-07
[patent_title] => 'Semiconductor integrated circuit and digital camera comprising the same'
[patent_app_type] => B1
[patent_app_number] => 09/666477
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[pdf_file] => patents/06/504/06504187.pdf
[firstpage_image] =>[orig_patent_app_number] => 09666477
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/666477 | Semiconductor integrated circuit and digital camera comprising the same | Sep 19, 2000 | Issued |
Array
(
[id] => 1395216
[patent_doc_number] => 06548838
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-15
[patent_title] => 'Field-effect transistor, bipolar transistor, and methods of fabricating the same'
[patent_app_type] => B1
[patent_app_number] => 09/666157
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[patent_app_date] => 2000-09-19
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[firstpage_image] =>[orig_patent_app_number] => 09666157
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/666157 | Field-effect transistor, bipolar transistor, and methods of fabricating the same | Sep 18, 2000 | Issued |
Array
(
[id] => 1476322
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[patent_title] => 'Semiconductor device and method of manufacturing the same'
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[pdf_file] => patents/06/388/06388295.pdf
[firstpage_image] =>[orig_patent_app_number] => 09663717
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/663717 | Semiconductor device and method of manufacturing the same | Sep 17, 2000 | Issued |
Array
(
[id] => 1455343
[patent_doc_number] => 06462361
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[patent_issue_date] => 2002-10-08
[patent_title] => 'GaInP epitaxial stacking structure and fabrication method thereof, and a FET transistor using this structure'
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[firstpage_image] =>[orig_patent_app_number] => 09662587
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/662587 | GaInP epitaxial stacking structure and fabrication method thereof, and a FET transistor using this structure | Sep 14, 2000 | Issued |