| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 4410804
[patent_doc_number] => 06232636
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-15
[patent_title] => 'Lateral thin-film silicon-on-insulator (SOI) device having multiple doping profile slopes in the drift region'
[patent_app_type] => 1
[patent_app_number] => 9/200110
[patent_app_country] => US
[patent_app_date] => 1998-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 2336
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 276
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/232/06232636.pdf
[firstpage_image] =>[orig_patent_app_number] => 200110
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/200110 | Lateral thin-film silicon-on-insulator (SOI) device having multiple doping profile slopes in the drift region | Nov 24, 1998 | Issued |
Array
(
[id] => 4103106
[patent_doc_number] => 06049113
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-11
[patent_title] => 'Semiconductor device and semiconductor device manufacturing method'
[patent_app_type] => 1
[patent_app_number] => 9/199390
[patent_app_country] => US
[patent_app_date] => 1998-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 19
[patent_no_of_words] => 6629
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 221
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/049/06049113.pdf
[firstpage_image] =>[orig_patent_app_number] => 199390
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/199390 | Semiconductor device and semiconductor device manufacturing method | Nov 24, 1998 | Issued |
Array
(
[id] => 4309488
[patent_doc_number] => 06188103
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-13
[patent_title] => 'Method of forming sharp beak of poly by nitrogen implant to improve erase speed for split-gate flash'
[patent_app_type] => 1
[patent_app_number] => 9/196600
[patent_app_country] => US
[patent_app_date] => 1998-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 10
[patent_no_of_words] => 3339
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/188/06188103.pdf
[firstpage_image] =>[orig_patent_app_number] => 196600
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/196600 | Method of forming sharp beak of poly by nitrogen implant to improve erase speed for split-gate flash | Nov 19, 1998 | Issued |
Array
(
[id] => 7643556
[patent_doc_number] => 06429485
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-06
[patent_title] => 'Thin film transistor and method of fabricating thereof'
[patent_app_type] => B1
[patent_app_number] => 09/192050
[patent_app_country] => US
[patent_app_date] => 1998-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 24
[patent_no_of_words] => 5629
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 6
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/429/06429485.pdf
[firstpage_image] =>[orig_patent_app_number] => 09192050
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/192050 | Thin film transistor and method of fabricating thereof | Nov 12, 1998 | Issued |
| 09/191120 | SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SAME | Nov 12, 1998 | Abandoned |
Array
(
[id] => 4282511
[patent_doc_number] => 06281553
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-28
[patent_title] => 'Semiconductor device, electrostatic discharge protection device, and dielectric breakdown preventing method'
[patent_app_type] => 1
[patent_app_number] => 9/190827
[patent_app_country] => US
[patent_app_date] => 1998-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3107
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/281/06281553.pdf
[firstpage_image] =>[orig_patent_app_number] => 190827
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/190827 | Semiconductor device, electrostatic discharge protection device, and dielectric breakdown preventing method | Nov 11, 1998 | Issued |
Array
(
[id] => 4389524
[patent_doc_number] => 06262436
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-17
[patent_title] => 'Semiconductor device and method of making the same'
[patent_app_type] => 1
[patent_app_number] => 9/185640
[patent_app_country] => US
[patent_app_date] => 1998-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 3418
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/262/06262436.pdf
[firstpage_image] =>[orig_patent_app_number] => 185640
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/185640 | Semiconductor device and method of making the same | Nov 3, 1998 | Issued |
Array
(
[id] => 4292520
[patent_doc_number] => 06268637
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-31
[patent_title] => 'Method of making air gap isolation by making a lateral EPI bridge for low K isolation advanced CMOS fabrication'
[patent_app_type] => 1
[patent_app_number] => 9/178080
[patent_app_country] => US
[patent_app_date] => 1998-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 4915
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/268/06268637.pdf
[firstpage_image] =>[orig_patent_app_number] => 178080
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/178080 | Method of making air gap isolation by making a lateral EPI bridge for low K isolation advanced CMOS fabrication | Oct 21, 1998 | Issued |
Array
(
[id] => 4242648
[patent_doc_number] => 06144075
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-07
[patent_title] => 'CMOS inverter using gate induced drain leakage current'
[patent_app_type] => 1
[patent_app_number] => 9/177787
[patent_app_country] => US
[patent_app_date] => 1998-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 2075
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/144/06144075.pdf
[firstpage_image] =>[orig_patent_app_number] => 177787
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/177787 | CMOS inverter using gate induced drain leakage current | Oct 21, 1998 | Issued |
Array
(
[id] => 4301493
[patent_doc_number] => 06198151
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-06
[patent_title] => 'Semiconductor device, semiconductor integrated circuit device, and method of manufacturing same'
[patent_app_type] => 1
[patent_app_number] => 9/176417
[patent_app_country] => US
[patent_app_date] => 1998-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 20
[patent_no_of_words] => 9711
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/198/06198151.pdf
[firstpage_image] =>[orig_patent_app_number] => 176417
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/176417 | Semiconductor device, semiconductor integrated circuit device, and method of manufacturing same | Oct 20, 1998 | Issued |
Array
(
[id] => 4222329
[patent_doc_number] => 06111292
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-29
[patent_title] => 'Semiconductor fabrication employing self-aligned sidewall spacers laterally adjacent to a transistor gate'
[patent_app_type] => 1
[patent_app_number] => 9/175800
[patent_app_country] => US
[patent_app_date] => 1998-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 17
[patent_no_of_words] => 5060
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/111/06111292.pdf
[firstpage_image] =>[orig_patent_app_number] => 175800
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/175800 | Semiconductor fabrication employing self-aligned sidewall spacers laterally adjacent to a transistor gate | Oct 19, 1998 | Issued |
Array
(
[id] => 1452291
[patent_doc_number] => 06455918
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-09-24
[patent_title] => 'Integrated circuitry'
[patent_app_type] => B2
[patent_app_number] => 09/175049
[patent_app_country] => US
[patent_app_date] => 1998-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 2579
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 293
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/455/06455918.pdf
[firstpage_image] =>[orig_patent_app_number] => 09175049
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/175049 | Integrated circuitry | Oct 18, 1998 | Issued |
| 09/170957 | SELF-ALIGNED GATE AND METHOD | Oct 12, 1998 | Abandoned |
Array
(
[id] => 1468550
[patent_doc_number] => 06459132
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-10-01
[patent_title] => 'Image sensing device and production process thereof'
[patent_app_type] => B1
[patent_app_number] => 09/167577
[patent_app_country] => US
[patent_app_date] => 1998-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 29
[patent_no_of_words] => 4637
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/459/06459132.pdf
[firstpage_image] =>[orig_patent_app_number] => 09167577
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/167577 | Image sensing device and production process thereof | Oct 6, 1998 | Issued |
Array
(
[id] => 4413710
[patent_doc_number] => 06310376
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-30
[patent_title] => 'Semiconductor storage device capable of improving controllability of density and size of floating gate'
[patent_app_type] => 1
[patent_app_number] => 9/165800
[patent_app_country] => US
[patent_app_date] => 1998-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 18
[patent_no_of_words] => 6553
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 211
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/310/06310376.pdf
[firstpage_image] =>[orig_patent_app_number] => 165800
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/165800 | Semiconductor storage device capable of improving controllability of density and size of floating gate | Oct 1, 1998 | Issued |
Array
(
[id] => 3950060
[patent_doc_number] => 05990518
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-23
[patent_title] => 'MOS device'
[patent_app_type] => 1
[patent_app_number] => 9/164487
[patent_app_country] => US
[patent_app_date] => 1998-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 3646
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 210
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/990/05990518.pdf
[firstpage_image] =>[orig_patent_app_number] => 164487
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/164487 | MOS device | Sep 30, 1998 | Issued |
Array
(
[id] => 1448159
[patent_doc_number] => 06369456
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-09
[patent_title] => 'Semiconductor device and producing method thereof'
[patent_app_type] => B1
[patent_app_number] => 09/162787
[patent_app_country] => US
[patent_app_date] => 1998-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 3010
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/369/06369456.pdf
[firstpage_image] =>[orig_patent_app_number] => 09162787
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/162787 | Semiconductor device and producing method thereof | Sep 29, 1998 | Issued |
Array
(
[id] => 4294125
[patent_doc_number] => 06211555
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-03
[patent_title] => 'Semiconductor device with a pair of transistors having dual work function gate electrodes'
[patent_app_type] => 1
[patent_app_number] => 9/162407
[patent_app_country] => US
[patent_app_date] => 1998-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 24
[patent_no_of_words] => 5187
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/211/06211555.pdf
[firstpage_image] =>[orig_patent_app_number] => 162407
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/162407 | Semiconductor device with a pair of transistors having dual work function gate electrodes | Sep 28, 1998 | Issued |
| 09/159905 | SEMICONDUCTOR FABRICATION EMPLOYING A POST-IMPLANT ANNEAL WITHIN A LOW TEMPERATURE, HIGH PRESSURE NITROGEN AMBIENT TO IMPROVE CHANNEL AND GATE OXIDE RELIABILITY | Sep 23, 1998 | Abandoned |
Array
(
[id] => 4336759
[patent_doc_number] => 06313506
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-06
[patent_title] => 'Silicon-on-insulator field effect transistor'
[patent_app_type] => 1
[patent_app_number] => 9/157660
[patent_app_country] => US
[patent_app_date] => 1998-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 7
[patent_no_of_words] => 2010
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/313/06313506.pdf
[firstpage_image] =>[orig_patent_app_number] => 157660
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/157660 | Silicon-on-insulator field effect transistor | Sep 20, 1998 | Issued |