
Kriellion Antionette Sanders
Examiner (ID: 8649)
| Most Active Art Unit | 1714 |
| Art Unit(s) | 1761, 1768, 1503, 1511, 1714, 1796, 1509 |
| Total Applications | 2736 |
| Issued Applications | 2061 |
| Pending Applications | 79 |
| Abandoned Applications | 597 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4086957
[patent_doc_number] => 06054751
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-25
[patent_title] => 'Semiconductor integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 8/932623
[patent_app_country] => US
[patent_app_date] => 1997-09-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 4072
[patent_no_of_claims] => 11
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/054/06054751.pdf
[firstpage_image] =>[orig_patent_app_number] => 932623
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/932623 | Semiconductor integrated circuit | Sep 16, 1997 | Issued |
Array
(
[id] => 3938955
[patent_doc_number] => 05939761
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-17
[patent_title] => 'Method of forming a field effect transistor'
[patent_app_type] => 1
[patent_app_number] => 8/929693
[patent_app_country] => US
[patent_app_date] => 1997-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 2059
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[pdf_file] => patents/05/939/05939761.pdf
[firstpage_image] =>[orig_patent_app_number] => 929693
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/929693 | Method of forming a field effect transistor | Sep 14, 1997 | Issued |
Array
(
[id] => 3801929
[patent_doc_number] => 05828106
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-27
[patent_title] => 'ESD tolerated SOI device'
[patent_app_type] => 1
[patent_app_number] => 8/915140
[patent_app_country] => US
[patent_app_date] => 1997-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 16
[patent_no_of_words] => 4254
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[pdf_file] => patents/05/828/05828106.pdf
[firstpage_image] =>[orig_patent_app_number] => 915140
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/915140 | ESD tolerated SOI device | Aug 19, 1997 | Issued |
Array
(
[id] => 4031903
[patent_doc_number] => 05903054
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-11
[patent_title] => 'Integrated circuit with improved pre-metal planarization'
[patent_app_type] => 1
[patent_app_number] => 8/915195
[patent_app_country] => US
[patent_app_date] => 1997-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2475
[patent_no_of_claims] => 27
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[patent_words_short_claim] => 170
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/903/05903054.pdf
[firstpage_image] =>[orig_patent_app_number] => 915195
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/915195 | Integrated circuit with improved pre-metal planarization | Aug 19, 1997 | Issued |
Array
(
[id] => 3892046
[patent_doc_number] => 05894145
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-13
[patent_title] => 'Multiple substrate bias random access memory device'
[patent_app_type] => 1
[patent_app_number] => 8/909904
[patent_app_country] => US
[patent_app_date] => 1997-08-12
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 1182
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[pdf_file] => patents/05/894/05894145.pdf
[firstpage_image] =>[orig_patent_app_number] => 909904
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/909904 | Multiple substrate bias random access memory device | Aug 11, 1997 | Issued |
Array
(
[id] => 4086675
[patent_doc_number] => 06054733
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-25
[patent_title] => 'Method for fabricating a flash EEPROM'
[patent_app_type] => 1
[patent_app_number] => 8/909713
[patent_app_country] => US
[patent_app_date] => 1997-08-12
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[pdf_file] => patents/06/054/06054733.pdf
[firstpage_image] =>[orig_patent_app_number] => 909713
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/909713 | Method for fabricating a flash EEPROM | Aug 11, 1997 | Issued |
Array
(
[id] => 4222921
[patent_doc_number] => 06087708
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-11
[patent_title] => 'Semiconductor integrated circuit device and a method of producing the same'
[patent_app_type] => 1
[patent_app_number] => 8/907477
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[patent_app_date] => 1997-08-11
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[pdf_file] => patents/06/087/06087708.pdf
[firstpage_image] =>[orig_patent_app_number] => 907477
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/907477 | Semiconductor integrated circuit device and a method of producing the same | Aug 10, 1997 | Issued |
Array
(
[id] => 4119808
[patent_doc_number] => 06046473
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-04
[patent_title] => 'Structure and process for reducing the on-resistance of MOS-gated power devices'
[patent_app_type] => 1
[patent_app_number] => 8/905754
[patent_app_country] => US
[patent_app_date] => 1997-08-04
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/046/06046473.pdf
[firstpage_image] =>[orig_patent_app_number] => 905754
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/905754 | Structure and process for reducing the on-resistance of MOS-gated power devices | Aug 3, 1997 | Issued |
Array
(
[id] => 4016910
[patent_doc_number] => 05962884
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-05
[patent_title] => 'Single transistor ferroelectric memory cell with asymmetrical ferroelectric polarization and method of making the same'
[patent_app_type] => 1
[patent_app_number] => 8/905380
[patent_app_country] => US
[patent_app_date] => 1997-08-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/05/962/05962884.pdf
[firstpage_image] =>[orig_patent_app_number] => 905380
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/905380 | Single transistor ferroelectric memory cell with asymmetrical ferroelectric polarization and method of making the same | Aug 3, 1997 | Issued |
Array
(
[id] => 3944767
[patent_doc_number] => 05973401
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-26
[patent_title] => 'Semiconductor device enabling temperature control in the chip thereof'
[patent_app_type] => 1
[patent_app_number] => 8/892203
[patent_app_country] => US
[patent_app_date] => 1997-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
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[patent_no_of_words] => 8033
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[pdf_file] => patents/05/973/05973401.pdf
[firstpage_image] =>[orig_patent_app_number] => 892203
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/892203 | Semiconductor device enabling temperature control in the chip thereof | Jul 13, 1997 | Issued |
Array
(
[id] => 4209949
[patent_doc_number] => 06078082
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-20
[patent_title] => 'Field-effect transistor having multi-part channel'
[patent_app_type] => 1
[patent_app_number] => 8/893628
[patent_app_country] => US
[patent_app_date] => 1997-07-11
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[pdf_file] => patents/06/078/06078082.pdf
[firstpage_image] =>[orig_patent_app_number] => 893628
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/893628 | Field-effect transistor having multi-part channel | Jul 10, 1997 | Issued |
Array
(
[id] => 3972297
[patent_doc_number] => 05886373
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[patent_title] => 'Field effect transistor'
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Array
(
[id] => 4123355
[patent_doc_number] => 06072209
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-06
[patent_title] => 'Four F.sup.2 folded bit line DRAM cell structure having buried bit and word lines'
[patent_app_type] => 1
[patent_app_number] => 8/889463
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[pdf_file] => patents/06/072/06072209.pdf
[firstpage_image] =>[orig_patent_app_number] => 889463
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/889463 | Four F.sup.2 folded bit line DRAM cell structure having buried bit and word lines | Jul 7, 1997 | Issued |
Array
(
[id] => 3972158
[patent_doc_number] => 05886364
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Array
(
[id] => 4254623
[patent_doc_number] => 06222238
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[patent_issue_date] => 2001-04-24
[patent_title] => 'Low voltage CMOS process and device with individually adjustable LDD spacers'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/887459 | Low voltage CMOS process and device with individually adjustable LDD spacers | Jul 1, 1997 | Issued |
Array
(
[id] => 4301282
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/885286 | Analogue misfet with threshold voltage adjuster | Jun 29, 1997 | Issued |
Array
(
[id] => 4179737
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Array
(
[id] => 4101438
[patent_doc_number] => 06097052
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Array
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Array
(
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[firstpage_image] =>[orig_patent_app_number] => 880508
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/880508 | Semiconductor device and method of fabricating the same | Jun 22, 1997 | Issued |