
Kristina N. S. Junge
Examiner (ID: 17134, Phone: (571)270-7816 , Office: P/3638 )
| Most Active Art Unit | 3638 |
| Art Unit(s) | 3700, 3631, 3638, 3611 |
| Total Applications | 708 |
| Issued Applications | 343 |
| Pending Applications | 10 |
| Abandoned Applications | 357 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4258369
[patent_doc_number] => 06258634
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-10
[patent_title] => 'Method for manufacturing a dual-direction over-voltage and over-current IC protection device and its cell structure'
[patent_app_type] => 1
[patent_app_number] => 9/246035
[patent_app_country] => US
[patent_app_date] => 1999-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 21
[patent_no_of_words] => 5022
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/258/06258634.pdf
[firstpage_image] =>[orig_patent_app_number] => 246035
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/246035 | Method for manufacturing a dual-direction over-voltage and over-current IC protection device and its cell structure | Feb 3, 1999 | Issued |
Array
(
[id] => 4414201
[patent_doc_number] => 06229180
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-08
[patent_title] => 'MOS type semiconductor apparatus'
[patent_app_type] => 1
[patent_app_number] => 9/238855
[patent_app_country] => US
[patent_app_date] => 1999-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 24
[patent_no_of_words] => 13342
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[patent_words_short_claim] => 201
[patent_maintenance] => 1
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[pdf_file] => patents/06/229/06229180.pdf
[firstpage_image] =>[orig_patent_app_number] => 238855
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/238855 | MOS type semiconductor apparatus | Jan 26, 1999 | Issued |
Array
(
[id] => 4293601
[patent_doc_number] => 06184062
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-06
[patent_title] => 'Process for forming cone shaped solder for chip interconnection'
[patent_app_type] => 1
[patent_app_number] => 9/233383
[patent_app_country] => US
[patent_app_date] => 1999-01-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 4912
[patent_no_of_claims] => 71
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 87
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/184/06184062.pdf
[firstpage_image] =>[orig_patent_app_number] => 233383
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/233383 | Process for forming cone shaped solder for chip interconnection | Jan 18, 1999 | Issued |
Array
(
[id] => 4246510
[patent_doc_number] => 06221691
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-24
[patent_title] => 'Method and system for attaching semiconductor dice to substrates'
[patent_app_type] => 1
[patent_app_number] => 9/232442
[patent_app_country] => US
[patent_app_date] => 1999-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 9
[patent_no_of_words] => 3502
[patent_no_of_claims] => 21
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/221/06221691.pdf
[firstpage_image] =>[orig_patent_app_number] => 232442
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/232442 | Method and system for attaching semiconductor dice to substrates | Jan 14, 1999 | Issued |
Array
(
[id] => 4162771
[patent_doc_number] => 06157065
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-05
[patent_title] => 'Electrostatic discharge protective circuit under conductive pad'
[patent_app_type] => 1
[patent_app_number] => 9/232204
[patent_app_country] => US
[patent_app_date] => 1999-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 2170
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[pdf_file] => patents/06/157/06157065.pdf
[firstpage_image] =>[orig_patent_app_number] => 232204
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/232204 | Electrostatic discharge protective circuit under conductive pad | Jan 13, 1999 | Issued |
Array
(
[id] => 4259046
[patent_doc_number] => 06204175
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-20
[patent_title] => 'Method of depositing a smooth conformal aluminum film on a refractory metal nitride layer'
[patent_app_type] => 1
[patent_app_number] => 9/226053
[patent_app_country] => US
[patent_app_date] => 1999-01-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 2997
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[pdf_file] => patents/06/204/06204175.pdf
[firstpage_image] =>[orig_patent_app_number] => 226053
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/226053 | Method of depositing a smooth conformal aluminum film on a refractory metal nitride layer | Jan 4, 1999 | Issued |
Array
(
[id] => 4359299
[patent_doc_number] => 06291887
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-18
[patent_title] => 'Dual damascene arrangements for metal interconnection with low k dielectric constant materials and nitride middle etch stop layer'
[patent_app_type] => 1
[patent_app_number] => 9/225220
[patent_app_country] => US
[patent_app_date] => 1999-01-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 11
[patent_no_of_words] => 4160
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[pdf_file] => patents/06/291/06291887.pdf
[firstpage_image] =>[orig_patent_app_number] => 225220
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/225220 | Dual damascene arrangements for metal interconnection with low k dielectric constant materials and nitride middle etch stop layer | Jan 3, 1999 | Issued |
Array
(
[id] => 4246497
[patent_doc_number] => 06221690
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-24
[patent_title] => 'Semiconductor package and production method thereof'
[patent_app_type] => 1
[patent_app_number] => 9/215190
[patent_app_country] => US
[patent_app_date] => 1998-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 4590
[patent_no_of_claims] => 12
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/221/06221690.pdf
[firstpage_image] =>[orig_patent_app_number] => 215190
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/215190 | Semiconductor package and production method thereof | Dec 17, 1998 | Issued |
Array
(
[id] => 4381502
[patent_doc_number] => 06277726
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-21
[patent_title] => 'Method for decreasing contact resistance of an electrode positioned inside a misaligned via for multilevel interconnects'
[patent_app_type] => 1
[patent_app_number] => 9/208202
[patent_app_country] => US
[patent_app_date] => 1998-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 4364
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[pdf_file] => patents/06/277/06277726.pdf
[firstpage_image] =>[orig_patent_app_number] => 208202
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/208202 | Method for decreasing contact resistance of an electrode positioned inside a misaligned via for multilevel interconnects | Dec 8, 1998 | Issued |
Array
(
[id] => 4292661
[patent_doc_number] => 06180507
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-30
[patent_title] => 'Method of forming interconnections'
[patent_app_type] => 1
[patent_app_number] => 9/206052
[patent_app_country] => US
[patent_app_date] => 1998-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/06/180/06180507.pdf
[firstpage_image] =>[orig_patent_app_number] => 206052
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/206052 | Method of forming interconnections | Dec 3, 1998 | Issued |
Array
(
[id] => 4407554
[patent_doc_number] => 06239015
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-29
[patent_title] => 'Semiconductor device having polysilicon interconnections and method of making same'
[patent_app_type] => 1
[patent_app_number] => 9/204363
[patent_app_country] => US
[patent_app_date] => 1998-12-04
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/239/06239015.pdf
[firstpage_image] =>[orig_patent_app_number] => 204363
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/204363 | Semiconductor device having polysilicon interconnections and method of making same | Dec 3, 1998 | Issued |
Array
(
[id] => 4290203
[patent_doc_number] => 06235626
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-22
[patent_title] => 'Method of forming a gate electrode using an insulating film with an opening pattern'
[patent_app_type] => 1
[patent_app_number] => 9/201151
[patent_app_country] => US
[patent_app_date] => 1998-11-30
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[patent_drawing_sheets_cnt] => 55
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[pdf_file] => patents/06/235/06235626.pdf
[firstpage_image] =>[orig_patent_app_number] => 201151
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/201151 | Method of forming a gate electrode using an insulating film with an opening pattern | Nov 29, 1998 | Issued |
Array
(
[id] => 1550268
[patent_doc_number] => 06399432
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-04
[patent_title] => 'Process to control poly silicon profiles in a dual doped poly silicon process'
[patent_app_type] => B1
[patent_app_number] => 09/199203
[patent_app_country] => US
[patent_app_date] => 1998-11-24
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[pdf_file] => patents/06/399/06399432.pdf
[firstpage_image] =>[orig_patent_app_number] => 09199203
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/199203 | Process to control poly silicon profiles in a dual doped poly silicon process | Nov 23, 1998 | Issued |
Array
(
[id] => 4299714
[patent_doc_number] => 06180971
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[patent_issue_date] => 2001-01-30
[patent_title] => 'Capacitor and method of manufacturing the same'
[patent_app_type] => 1
[patent_app_number] => 9/197919
[patent_app_country] => US
[patent_app_date] => 1998-11-23
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/180/06180971.pdf
[firstpage_image] =>[orig_patent_app_number] => 197919
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/197919 | Capacitor and method of manufacturing the same | Nov 22, 1998 | Issued |
Array
(
[id] => 4130566
[patent_doc_number] => 06146918
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[patent_kind] => NA
[patent_issue_date] => 2000-11-14
[patent_title] => 'Method of fabricating a semiconductor package'
[patent_app_type] => 1
[patent_app_number] => 9/195996
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[pdf_file] => patents/06/146/06146918.pdf
[firstpage_image] =>[orig_patent_app_number] => 195996
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/195996 | Method of fabricating a semiconductor package | Nov 19, 1998 | Issued |
Array
(
[id] => 4222099
[patent_doc_number] => 06111277
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-29
[patent_title] => 'Semiconductor device as well as light emitting semiconductor device'
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[patent_app_date] => 1998-10-21
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[pdf_file] => patents/06/111/06111277.pdf
[firstpage_image] =>[orig_patent_app_number] => 176270
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/176270 | Semiconductor device as well as light emitting semiconductor device | Oct 20, 1998 | Issued |
Array
(
[id] => 4287024
[patent_doc_number] => 06268275
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-31
[patent_title] => 'Method of locating conductive spheres utilizing screen and hopper of solder balls'
[patent_app_type] => 1
[patent_app_number] => 9/168621
[patent_app_country] => US
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[pdf_file] => patents/06/268/06268275.pdf
[firstpage_image] =>[orig_patent_app_number] => 168621
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/168621 | Method of locating conductive spheres utilizing screen and hopper of solder balls | Oct 7, 1998 | Issued |
Array
(
[id] => 4359004
[patent_doc_number] => 06169008
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[patent_issue_date] => 2001-01-02
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[pdf_file] => patents/06/169/06169008.pdf
[firstpage_image] =>[orig_patent_app_number] => 166680
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/166680 | High Q inductor and its forming method | Oct 4, 1998 | Issued |
Array
(
[id] => 4309354
[patent_doc_number] => 06188095
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-13
[patent_title] => '61/4 f2 DRAM cell structure with four nodes per bitline-stud and two topological wordline levels'
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[pdf_file] => patents/06/188/06188095.pdf
[firstpage_image] =>[orig_patent_app_number] => 163670
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/163670 | 61/4 f2 DRAM cell structure with four nodes per bitline-stud and two topological wordline levels | Sep 29, 1998 | Issued |
Array
(
[id] => 4389914
[patent_doc_number] => 06262465
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[patent_title] => 'Highly-doped P-type contact for high-speed, front-side illuminated photodiode'
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/262/06262465.pdf
[firstpage_image] =>[orig_patent_app_number] => 161097
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/161097 | Highly-doped P-type contact for high-speed, front-side illuminated photodiode | Sep 24, 1998 | Issued |