Search

Krystal Robinson

Examiner (ID: 8724, Phone: (571)272-9258 , Office: P/2847 )

Most Active Art Unit
2848
Art Unit(s)
2847, 2848
Total Applications
947
Issued Applications
790
Pending Applications
102
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6999656 [patent_doc_number] => 20050138330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'MAXQ microcontroller' [patent_app_type] => utility [patent_app_number] => 10/746877 [patent_app_country] => US [patent_app_date] => 2003-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6092 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20050138330.pdf [firstpage_image] =>[orig_patent_app_number] => 10746877 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/746877
MAXQ microcontroller Dec 22, 2003 Abandoned
Array ( [id] => 7107249 [patent_doc_number] => 20050108503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-19 [patent_title] => 'Two dimensional addressing of a matrix-vector register array' [patent_app_type] => utility [patent_app_number] => 10/715688 [patent_app_country] => US [patent_app_date] => 2003-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7207 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20050108503.pdf [firstpage_image] =>[orig_patent_app_number] => 10715688 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/715688
Two dimensional addressing of a matrix-vector register array Nov 17, 2003 Issued
Array ( [id] => 7107261 [patent_doc_number] => 20050108509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-19 [patent_title] => 'Error detection method and system for processors that employs lockstepped concurrent threads' [patent_app_type] => utility [patent_app_number] => 10/714093 [patent_app_country] => US [patent_app_date] => 2003-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5740 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20050108509.pdf [firstpage_image] =>[orig_patent_app_number] => 10714093 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/714093
Error detection method and system for processors that employs lockstepped concurrent threads Nov 12, 2003 Abandoned
Array ( [id] => 6907079 [patent_doc_number] => 20050102474 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-12 [patent_title] => 'Dynamically caching engine instructions' [patent_app_type] => utility [patent_app_number] => 10/704432 [patent_app_country] => US [patent_app_date] => 2003-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4235 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20050102474.pdf [firstpage_image] =>[orig_patent_app_number] => 10704432 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/704432
Dynamically caching engine instructions Nov 5, 2003 Abandoned
Array ( [id] => 6907264 [patent_doc_number] => 20050102659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-12 [patent_title] => 'Methods and apparatus for setting up hardware loops in a deeply pipelined processor' [patent_app_type] => utility [patent_app_number] => 10/702363 [patent_app_country] => US [patent_app_date] => 2003-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6739 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20050102659.pdf [firstpage_image] =>[orig_patent_app_number] => 10702363 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/702363
Methods and apparatus for setting up hardware loops in a deeply pipelined processor Nov 5, 2003 Abandoned
Array ( [id] => 7451684 [patent_doc_number] => 20040268335 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'Modulo scheduling of multiple instruction chains' [patent_app_type] => new [patent_app_number] => 10/702990 [patent_app_country] => US [patent_app_date] => 2003-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8103 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20040268335.pdf [firstpage_image] =>[orig_patent_app_number] => 10702990 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/702990
Modulo scheduling of multiple instruction chains Nov 5, 2003 Abandoned
Array ( [id] => 414794 [patent_doc_number] => 07284117 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-10-16 [patent_title] => 'Processor that predicts floating point instruction latency based on predicted precision' [patent_app_type] => utility [patent_app_number] => 10/700391 [patent_app_country] => US [patent_app_date] => 2003-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8636 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/284/07284117.pdf [firstpage_image] =>[orig_patent_app_number] => 10700391 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/700391
Processor that predicts floating point instruction latency based on predicted precision Nov 3, 2003 Issued
Array ( [id] => 283973 [patent_doc_number] => 07555633 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-06-30 [patent_title] => 'Instruction cache prefetch based on trace cache eviction' [patent_app_type] => utility [patent_app_number] => 10/700033 [patent_app_country] => US [patent_app_date] => 2003-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7158 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/555/07555633.pdf [firstpage_image] =>[orig_patent_app_number] => 10700033 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/700033
Instruction cache prefetch based on trace cache eviction Nov 2, 2003 Issued
Array ( [id] => 7443133 [patent_doc_number] => 20040210748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-21 [patent_title] => 'Processor and method capable of executing conditional instructions' [patent_app_type] => new [patent_app_number] => 10/695812 [patent_app_country] => US [patent_app_date] => 2003-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2394 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20040210748.pdf [firstpage_image] =>[orig_patent_app_number] => 10695812 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/695812
Processor and method capable of executing conditional instructions Oct 29, 2003 Abandoned
Array ( [id] => 6919850 [patent_doc_number] => 20050097305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Method and apparatus for using FPGA technology with a microprocessor for reconfigurable, instruction level hardware acceleration' [patent_app_type] => utility [patent_app_number] => 10/696865 [patent_app_country] => US [patent_app_date] => 2003-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2779 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20050097305.pdf [firstpage_image] =>[orig_patent_app_number] => 10696865 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/696865
System for using FPGA technology with a microprocessor for reconfigurable, instruction level hardware acceleration Oct 29, 2003 Issued
Array ( [id] => 321343 [patent_doc_number] => 07523292 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-21 [patent_title] => 'Array-type processor having state control units controlling a plurality of processor elements arranged in a matrix' [patent_app_type] => utility [patent_app_number] => 10/682830 [patent_app_country] => US [patent_app_date] => 2003-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 26 [patent_no_of_words] => 8221 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/523/07523292.pdf [firstpage_image] =>[orig_patent_app_number] => 10682830 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/682830
Array-type processor having state control units controlling a plurality of processor elements arranged in a matrix Oct 9, 2003 Issued
Array ( [id] => 929623 [patent_doc_number] => 07315935 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-01-01 [patent_title] => 'Apparatus and method for port arbitration in a register file on the basis of functional unit issue slots' [patent_app_type] => utility [patent_app_number] => 10/679745 [patent_app_country] => US [patent_app_date] => 2003-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 8593 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/315/07315935.pdf [firstpage_image] =>[orig_patent_app_number] => 10679745 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/679745
Apparatus and method for port arbitration in a register file on the basis of functional unit issue slots Oct 5, 2003 Issued
Array ( [id] => 7118863 [patent_doc_number] => 20050071610 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-31 [patent_title] => 'Method and apparatus for debug support for individual instructions and memory locations' [patent_app_type] => utility [patent_app_number] => 10/675751 [patent_app_country] => US [patent_app_date] => 2003-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 15266 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0071/20050071610.pdf [firstpage_image] =>[orig_patent_app_number] => 10675751 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/675751
Method and apparatus for debug support for individual instructions and memory locations Sep 29, 2003 Abandoned
Array ( [id] => 7129142 [patent_doc_number] => 20050060524 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-17 [patent_title] => 'Processor and methods for micro-operations generation' [patent_app_type] => utility [patent_app_number] => 10/663832 [patent_app_country] => US [patent_app_date] => 2003-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4953 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20050060524.pdf [firstpage_image] =>[orig_patent_app_number] => 10663832 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/663832
Processor and methods for micro-operations generation Sep 16, 2003 Abandoned
Array ( [id] => 7085154 [patent_doc_number] => 20050050534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-03 [patent_title] => 'Methods and apparatus to pre-execute instructions on a single thread' [patent_app_type] => utility [patent_app_number] => 10/653602 [patent_app_country] => US [patent_app_date] => 2003-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4006 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20050050534.pdf [firstpage_image] =>[orig_patent_app_number] => 10653602 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/653602
Methods and apparatus to pre-execute instructions on a single thread Sep 1, 2003 Abandoned
Array ( [id] => 7084926 [patent_doc_number] => 20050050306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-03 [patent_title] => 'Executing instructions on a processor' [patent_app_type] => utility [patent_app_number] => 10/649356 [patent_app_country] => US [patent_app_date] => 2003-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4447 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20050050306.pdf [firstpage_image] =>[orig_patent_app_number] => 10649356 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/649356
Executing instructions on a processor Aug 25, 2003 Abandoned
Array ( [id] => 7312622 [patent_doc_number] => 20040143727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-22 [patent_title] => 'Method and apparatus for correcting an internal call/return stack in a microprocessor that detects from multiple pipeline stages incorrect speculative update of the call/return stack' [patent_app_type] => new [patent_app_number] => 10/643338 [patent_app_country] => US [patent_app_date] => 2003-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8600 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0143/20040143727.pdf [firstpage_image] =>[orig_patent_app_number] => 10643338 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/643338
Method and apparatus for correcting an internal call/return stack in a microprocessor that detects from multiple pipeline stages incorrect speculative update of the call/return stack Aug 18, 2003 Issued
Array ( [id] => 882207 [patent_doc_number] => 07360070 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-04-15 [patent_title] => 'Specialized processing upon an occurrence of an exceptional situation during the course of a computation' [patent_app_type] => utility [patent_app_number] => 10/641215 [patent_app_country] => US [patent_app_date] => 2003-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3052 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/360/07360070.pdf [firstpage_image] =>[orig_patent_app_number] => 10641215 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/641215
Specialized processing upon an occurrence of an exceptional situation during the course of a computation Aug 12, 2003 Issued
Array ( [id] => 7440444 [patent_doc_number] => 20040162967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-19 [patent_title] => 'Start transactional execution (STE) instruction to support transactional program execution' [patent_app_type] => new [patent_app_number] => 10/637166 [patent_app_country] => US [patent_app_date] => 2003-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5489 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20040162967.pdf [firstpage_image] =>[orig_patent_app_number] => 10637166 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/637166
Method for reducing lock manipulation overhead during access to critical code sections Aug 7, 2003 Issued
Array ( [id] => 922547 [patent_doc_number] => 07321964 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-22 [patent_title] => 'Store-to-load forwarding buffer using indexed lookup' [patent_app_type] => utility [patent_app_number] => 10/615101 [patent_app_country] => US [patent_app_date] => 2003-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7699 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/321/07321964.pdf [firstpage_image] =>[orig_patent_app_number] => 10615101 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/615101
Store-to-load forwarding buffer using indexed lookup Jul 7, 2003 Issued
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