Search

Kyle M. Riddle

Examiner (ID: 16842)

Most Active Art Unit
3748
Art Unit(s)
3748
Total Applications
452
Issued Applications
387
Pending Applications
7
Abandoned Applications
58

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9912003 [patent_doc_number] => 20150067206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'MULTI-PROTOCOL SERIAL COMMUNICATION INTERFACE' [patent_app_type] => utility [patent_app_number] => 14/014128 [patent_app_country] => US [patent_app_date] => 2013-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3726 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14014128 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/014128
Multi-protocol serial communication interface Aug 28, 2013 Issued
Array ( [id] => 11416766 [patent_doc_number] => 09563593 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-07 [patent_title] => 'Peripheral component interconnect adapter and computer using same' [patent_app_type] => utility [patent_app_number] => 14/012949 [patent_app_country] => US [patent_app_date] => 2013-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1606 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14012949 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/012949
Peripheral component interconnect adapter and computer using same Aug 27, 2013 Issued
Array ( [id] => 11752399 [patent_doc_number] => 09710411 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-18 [patent_title] => 'Signal conditioner' [patent_app_type] => utility [patent_app_number] => 13/963264 [patent_app_country] => US [patent_app_date] => 2013-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 7067 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13963264 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/963264
Signal conditioner Aug 8, 2013 Issued
Array ( [id] => 11226780 [patent_doc_number] => 09454503 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-09-27 [patent_title] => 'Hot swap decoupling for noise reduction and failure prevention' [patent_app_type] => utility [patent_app_number] => 13/963624 [patent_app_country] => US [patent_app_date] => 2013-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3027 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13963624 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/963624
Hot swap decoupling for noise reduction and failure prevention Aug 8, 2013 Issued
13/984428 SEMICONDUCTOR DEVICE Aug 7, 2013 Abandoned
Array ( [id] => 11786678 [patent_doc_number] => 09396113 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-19 [patent_title] => 'Flexible configuration hardware streaming unit' [patent_app_type] => utility [patent_app_number] => 13/960150 [patent_app_country] => US [patent_app_date] => 2013-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6980 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13960150 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/960150
Flexible configuration hardware streaming unit Aug 5, 2013 Issued
Array ( [id] => 11780866 [patent_doc_number] => 09390050 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-12 [patent_title] => 'Data transmission apparatus and method' [patent_app_type] => utility [patent_app_number] => 13/953305 [patent_app_country] => US [patent_app_date] => 2013-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3015 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13953305 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/953305
Data transmission apparatus and method Jul 28, 2013 Issued
Array ( [id] => 12011661 [patent_doc_number] => 09804980 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-31 [patent_title] => 'System management through direct communication between system management controllers' [patent_app_type] => utility [patent_app_number] => 13/950996 [patent_app_country] => US [patent_app_date] => 2013-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4803 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13950996 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/950996
System management through direct communication between system management controllers Jul 24, 2013 Issued
Array ( [id] => 11786710 [patent_doc_number] => 09396145 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-07-19 [patent_title] => 'In-chip bus tracer' [patent_app_type] => utility [patent_app_number] => 13/950654 [patent_app_country] => US [patent_app_date] => 2013-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3242 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13950654 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/950654
In-chip bus tracer Jul 24, 2013 Issued
Array ( [id] => 9137247 [patent_doc_number] => 20130297962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-07 [patent_title] => 'BRIDGE DEVICE' [patent_app_type] => utility [patent_app_number] => 13/935860 [patent_app_country] => US [patent_app_date] => 2013-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1920 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13935860 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/935860
Bridge device Jul 4, 2013 Issued
Array ( [id] => 9398350 [patent_doc_number] => 20140095756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-03 [patent_title] => 'HIGH-SPEED DATA TRANSMISSION INTERFACE CIRCUIT AND DESIGN METHOD OF THE SAME' [patent_app_type] => utility [patent_app_number] => 13/900545 [patent_app_country] => US [patent_app_date] => 2013-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3180 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13900545 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/900545
High-speed data transmission interface circuit and design method of the same May 22, 2013 Issued
Array ( [id] => 9176291 [patent_doc_number] => 20130318276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-28 [patent_title] => 'OFFLOADING OF COMPUTATION FOR RACK LEVEL SERVERS AND CORRESPONDING METHODS AND SYSTEMS' [patent_app_type] => utility [patent_app_number] => 13/900241 [patent_app_country] => US [patent_app_date] => 2013-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5036 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13900241 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/900241
OFFLOADING OF COMPUTATION FOR RACK LEVEL SERVERS AND CORRESPONDING METHODS AND SYSTEMS May 21, 2013 Abandoned
Array ( [id] => 9176284 [patent_doc_number] => 20130318269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-28 [patent_title] => 'PROCESSING STRUCTURED AND UNSTRUCTURED DATA USING OFFLOAD PROCESSORS' [patent_app_type] => utility [patent_app_number] => 13/900333 [patent_app_country] => US [patent_app_date] => 2013-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 13673 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13900333 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/900333
PROCESSING STRUCTURED AND UNSTRUCTURED DATA USING OFFLOAD PROCESSORS May 21, 2013 Abandoned
Array ( [id] => 9176292 [patent_doc_number] => 20130318277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-28 [patent_title] => 'PROCESSING STRUCTURED AND UNSTRUCTURED DATA USING OFFLOAD PROCESSORS' [patent_app_type] => utility [patent_app_number] => 13/900318 [patent_app_country] => US [patent_app_date] => 2013-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 13671 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13900318 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/900318
Processing structured and unstructured data using offload processors May 21, 2013 Issued
Array ( [id] => 9853019 [patent_doc_number] => 08954767 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-10 [patent_title] => 'Standby current reduction through a switching arrangement with multiple regulators' [patent_app_type] => utility [patent_app_number] => 13/888099 [patent_app_country] => US [patent_app_date] => 2013-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 4870 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13888099 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/888099
Standby current reduction through a switching arrangement with multiple regulators May 5, 2013 Issued
Array ( [id] => 11786714 [patent_doc_number] => 09396149 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-19 [patent_title] => 'PCIE switch apparatus and method of controlling connection thereof' [patent_app_type] => utility [patent_app_number] => 13/837566 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5444 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13837566 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/837566
PCIE switch apparatus and method of controlling connection thereof Mar 14, 2013 Issued
Array ( [id] => 9745366 [patent_doc_number] => 20140281085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'METHOD, APPARATUS, SYSTEM FOR HYBRID LANE STALLING OR NO-LOCK BUS ARCHITECTURES' [patent_app_type] => utility [patent_app_number] => 13/835176 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9362 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13835176 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/835176
METHOD, APPARATUS, SYSTEM FOR HYBRID LANE STALLING OR NO-LOCK BUS ARCHITECTURES Mar 14, 2013 Abandoned
Array ( [id] => 11200213 [patent_doc_number] => 09430428 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-30 [patent_title] => 'Circuit and method for software tracing' [patent_app_type] => utility [patent_app_number] => 13/833392 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4761 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 359 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13833392 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/833392
Circuit and method for software tracing Mar 14, 2013 Issued
Array ( [id] => 9745348 [patent_doc_number] => 20140281067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'Apparatus, system, and method for performing link training and equalization' [patent_app_type] => utility [patent_app_number] => 13/815916 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 14136 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13815916 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/815916
Apparatus, system, and method for performing link training and equalization Mar 14, 2013 Abandoned
Array ( [id] => 8941774 [patent_doc_number] => 20130191571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-25 [patent_title] => 'METHOD AND SYSTEM FOR DYNAMICALLY PROGRAMMABLE SERIAL/PARALLEL BUS INTERFACE' [patent_app_type] => utility [patent_app_number] => 13/800693 [patent_app_country] => US [patent_app_date] => 2013-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4303 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13800693 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/800693
METHOD AND SYSTEM FOR DYNAMICALLY PROGRAMMABLE SERIAL/PARALLEL BUS INTERFACE Mar 12, 2013
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