Search

Kyle Vallecillo

Examiner (ID: 13968, Phone: (571)272-7716 , Office: P/2112 )

Most Active Art Unit
2112
Art Unit(s)
2112
Total Applications
757
Issued Applications
658
Pending Applications
0
Abandoned Applications
103

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15186467 [patent_doc_number] => 20190363825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-28 [patent_title] => BANDWIDTH CONSTRAINED COMMUNICATION SYSTEMS WITH OPTIMIZED LOW-DENSITY PARITY-CHECK CODES [patent_app_type] => utility [patent_app_number] => 16/418798 [patent_app_country] => US [patent_app_date] => 2019-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12529 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16418798 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/418798
Bandwidth constrained communication systems with optimized low-density parity-check codes May 20, 2019 Issued
Array ( [id] => 16355253 [patent_doc_number] => 10795764 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-06 [patent_title] => Method to deliver in-DRAM ECC information through DDR bus [patent_app_type] => utility [patent_app_number] => 16/411127 [patent_app_country] => US [patent_app_date] => 2019-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 14491 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16411127 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/411127
Method to deliver in-DRAM ECC information through DDR bus May 12, 2019 Issued
Array ( [id] => 14786245 [patent_doc_number] => 20190268020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => TRANSMITTER AND METHOD FOR GENERATING ADDITIONAL PARITY THEREOF [patent_app_type] => utility [patent_app_number] => 16/410554 [patent_app_country] => US [patent_app_date] => 2019-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 32741 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16410554 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/410554
Transmitter and method for generating additional parity thereof May 12, 2019 Issued
Array ( [id] => 16520799 [patent_doc_number] => 10872014 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-22 [patent_title] => Method to deliver in-DRAM ECC information through DDR bus [patent_app_type] => utility [patent_app_number] => 16/411122 [patent_app_country] => US [patent_app_date] => 2019-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 14490 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16411122 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/411122
Method to deliver in-DRAM ECC information through DDR bus May 12, 2019 Issued
Array ( [id] => 16520799 [patent_doc_number] => 10872014 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-22 [patent_title] => Method to deliver in-DRAM ECC information through DDR bus [patent_app_type] => utility [patent_app_number] => 16/411122 [patent_app_country] => US [patent_app_date] => 2019-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 14490 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16411122 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/411122
Method to deliver in-DRAM ECC information through DDR bus May 12, 2019 Issued
Array ( [id] => 16520799 [patent_doc_number] => 10872014 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-22 [patent_title] => Method to deliver in-DRAM ECC information through DDR bus [patent_app_type] => utility [patent_app_number] => 16/411122 [patent_app_country] => US [patent_app_date] => 2019-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 14490 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16411122 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/411122
Method to deliver in-DRAM ECC information through DDR bus May 12, 2019 Issued
Array ( [id] => 16520799 [patent_doc_number] => 10872014 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-22 [patent_title] => Method to deliver in-DRAM ECC information through DDR bus [patent_app_type] => utility [patent_app_number] => 16/411122 [patent_app_country] => US [patent_app_date] => 2019-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 14490 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16411122 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/411122
Method to deliver in-DRAM ECC information through DDR bus May 12, 2019 Issued
Array ( [id] => 16551688 [patent_doc_number] => 10884848 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-05 [patent_title] => Memory device, memory system including the same and operation method of the memory system [patent_app_type] => utility [patent_app_number] => 16/408673 [patent_app_country] => US [patent_app_date] => 2019-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 15801 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16408673 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/408673
Memory device, memory system including the same and operation method of the memory system May 9, 2019 Issued
Array ( [id] => 16438415 [patent_doc_number] => 20200355741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-12 [patent_title] => ELECTROSTATIC DISCHARGE VERIFICATION DURING BIOMETRIC SCAN FOR TERMINAL LOGIN [patent_app_type] => utility [patent_app_number] => 16/407357 [patent_app_country] => US [patent_app_date] => 2019-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10250 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16407357 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/407357
Electrostatic discharge verification during biometric scan for terminal login May 8, 2019 Issued
Array ( [id] => 15049049 [patent_doc_number] => 20190335529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-31 [patent_title] => METHODS AND APPARATUS FOR TWO-STAGE ACK/DTX DETECTION [patent_app_type] => utility [patent_app_number] => 16/384878 [patent_app_country] => US [patent_app_date] => 2019-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5656 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16384878 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/384878
Methods and apparatus for two-stage ACK/DTX detection Apr 14, 2019 Issued
Array ( [id] => 16758415 [patent_doc_number] => 10976963 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-13 [patent_title] => Probabilistically selecting storage units based on latency or throughput in a dispersed storage network [patent_app_type] => utility [patent_app_number] => 16/384102 [patent_app_country] => US [patent_app_date] => 2019-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 16041 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16384102 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/384102
Probabilistically selecting storage units based on latency or throughput in a dispersed storage network Apr 14, 2019 Issued
Array ( [id] => 14678305 [patent_doc_number] => 20190238267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => USING SLICE ROUTERS FOR IMPROVED STORAGE PLACEMENT DETERMINATION [patent_app_type] => utility [patent_app_number] => 16/380383 [patent_app_country] => US [patent_app_date] => 2019-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7171 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16380383 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/380383
Using slice routers for improved storage placement determination Apr 9, 2019 Issued
Array ( [id] => 16307400 [patent_doc_number] => 10776193 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-09-15 [patent_title] => Identifying an remediating correctable hardware errors [patent_app_type] => utility [patent_app_number] => 16/380581 [patent_app_country] => US [patent_app_date] => 2019-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6165 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16380581 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/380581
Identifying an remediating correctable hardware errors Apr 9, 2019 Issued
Array ( [id] => 16594577 [patent_doc_number] => 10903859 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-26 [patent_title] => Error detection by means of group errors [patent_app_type] => utility [patent_app_number] => 16/380089 [patent_app_country] => US [patent_app_date] => 2019-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 29825 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16380089 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/380089
Error detection by means of group errors Apr 9, 2019 Issued
Array ( [id] => 14906189 [patent_doc_number] => 20190296860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => DATA RECEIVING METHOD AND DEVICE, AND DATA SENDING METHOD AND DEVICE [patent_app_type] => utility [patent_app_number] => 16/374414 [patent_app_country] => US [patent_app_date] => 2019-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16545 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16374414 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/374414
Data receiving method and device, and data sending method and device Apr 2, 2019 Issued
Array ( [id] => 16202685 [patent_doc_number] => 10727873 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-07-28 [patent_title] => System and method for successive cancellation list decoding of polar codes [patent_app_type] => utility [patent_app_number] => 16/373434 [patent_app_country] => US [patent_app_date] => 2019-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8602 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16373434 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/373434
System and method for successive cancellation list decoding of polar codes Apr 1, 2019 Issued
Array ( [id] => 16363217 [patent_doc_number] => 20200319968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-08 [patent_title] => MAINTAINING A CONSISTENT LOGICAL DATA SIZE WITH VARIABLE PROTECTION STRIPE SIZE IN AN ARRAY OF INDEPENDENT DISKS SYSTEM [patent_app_type] => utility [patent_app_number] => 16/372762 [patent_app_country] => US [patent_app_date] => 2019-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8422 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16372762 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/372762
Maintaining a consistent logical data size with variable protection stripe size in an array of independent disks system Apr 1, 2019 Issued
Array ( [id] => 16567477 [patent_doc_number] => 10892858 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-12 [patent_title] => Chain broadcasting in vehicle-to-everything (V2X) communications [patent_app_type] => utility [patent_app_number] => 16/372887 [patent_app_country] => US [patent_app_date] => 2019-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10794 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16372887 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/372887
Chain broadcasting in vehicle-to-everything (V2X) communications Apr 1, 2019 Issued
Array ( [id] => 16347755 [patent_doc_number] => 20200312406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => SELF-HEALING DOT-PRODUCT ENGINE [patent_app_type] => utility [patent_app_number] => 16/364717 [patent_app_country] => US [patent_app_date] => 2019-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6132 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16364717 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/364717
Self-healing dot-product engine Mar 25, 2019 Issued
Array ( [id] => 16247439 [patent_doc_number] => 10746790 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-08-18 [patent_title] => Constrained pseudorandom test pattern for in-system logic built-in self-test [patent_app_type] => utility [patent_app_number] => 16/363382 [patent_app_country] => US [patent_app_date] => 2019-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5935 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16363382 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/363382
Constrained pseudorandom test pattern for in-system logic built-in self-test Mar 24, 2019 Issued
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