Search

Kyle Vallecillo

Examiner (ID: 13968, Phone: (571)272-7716 , Office: P/2112 )

Most Active Art Unit
2112
Art Unit(s)
2112
Total Applications
757
Issued Applications
658
Pending Applications
0
Abandoned Applications
103

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15313181 [patent_doc_number] => 10521295 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Low cost, hardened single board computer for command and data handling [patent_app_type] => utility [patent_app_number] => 15/985536 [patent_app_country] => US [patent_app_date] => 2018-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7799 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15985536 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/985536
Low cost, hardened single board computer for command and data handling May 20, 2018 Issued
Array ( [id] => 14091915 [patent_doc_number] => 10241862 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-26 [patent_title] => Erased memory page reconstruction using distributed coding for multiple dimensional parities [patent_app_type] => utility [patent_app_number] => 15/982964 [patent_app_country] => US [patent_app_date] => 2018-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9091 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15982964 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/982964
Erased memory page reconstruction using distributed coding for multiple dimensional parities May 16, 2018 Issued
Array ( [id] => 14065183 [patent_doc_number] => 10236907 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-19 [patent_title] => Forward error correction (FEC) emulator [patent_app_type] => utility [patent_app_number] => 15/981844 [patent_app_country] => US [patent_app_date] => 2018-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3017 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15981844 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/981844
Forward error correction (FEC) emulator May 15, 2018 Issued
Array ( [id] => 13558443 [patent_doc_number] => 20180330769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-15 [patent_title] => MEMORY BUFFER WITH DATA SCRAMBLING AND ERROR CORRECTION [patent_app_type] => utility [patent_app_number] => 15/978344 [patent_app_country] => US [patent_app_date] => 2018-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7172 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15978344 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/978344
Memory buffer with data scrambling and error correction May 13, 2018 Issued
Array ( [id] => 13560299 [patent_doc_number] => 20180331697 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-15 [patent_title] => NOMINAL COMPLEXITY AND WEIGHTED COMBINATIONS FOR POLAR CODE CONSTRUCTION [patent_app_type] => utility [patent_app_number] => 15/976439 [patent_app_country] => US [patent_app_date] => 2018-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19976 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15976439 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/976439
NOMINAL COMPLEXITY AND WEIGHTED COMBINATIONS FOR POLAR CODE CONSTRUCTION May 9, 2018 Abandoned
Array ( [id] => 16045851 [patent_doc_number] => 10684796 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-16 [patent_title] => Memory system and operating method thereof [patent_app_type] => utility [patent_app_number] => 15/976651 [patent_app_country] => US [patent_app_date] => 2018-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 12983 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15976651 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/976651
Memory system and operating method thereof May 9, 2018 Issued
Array ( [id] => 13486559 [patent_doc_number] => 20180294822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-11 [patent_title] => DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 15/965444 [patent_app_country] => US [patent_app_date] => 2018-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 35462 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15965444 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/965444
Data processing device and data processing method using low density parity check encoding for decreasing signal-to-noise power ratio Apr 26, 2018 Issued
Array ( [id] => 15518959 [patent_doc_number] => 10566073 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-18 [patent_title] => Test apparatus and semiconductor chip [patent_app_type] => utility [patent_app_number] => 15/956148 [patent_app_country] => US [patent_app_date] => 2018-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3082 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15956148 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/956148
Test apparatus and semiconductor chip Apr 17, 2018 Issued
Array ( [id] => 13501129 [patent_doc_number] => 20180302107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-18 [patent_title] => DATA PROCESSING DEVICE AND DATA PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 15/945361 [patent_app_country] => US [patent_app_date] => 2018-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 50993 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 1039 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15945361 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/945361
Data processing device and data processing method using low density parity check encoding for decreasing signal-to-noise power ratio Apr 3, 2018 Issued
Array ( [id] => 13318501 [patent_doc_number] => 20180210788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-26 [patent_title] => METHOD, MEMORY CONTROLLER, AND MEMORY SYSTEM FOR READING DATA STORED IN FLASH MEMORY [patent_app_type] => utility [patent_app_number] => 15/927069 [patent_app_country] => US [patent_app_date] => 2018-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14519 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15927069 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/927069
Method, memory controller, and memory system for reading data stored in flash memory Mar 19, 2018 Issued
Array ( [id] => 15104805 [patent_doc_number] => 10473721 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-11-12 [patent_title] => Data streaming for testing identical circuit blocks [patent_app_type] => utility [patent_app_number] => 15/925655 [patent_app_country] => US [patent_app_date] => 2018-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 10486 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 347 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15925655 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/925655
Data streaming for testing identical circuit blocks Mar 18, 2018 Issued
Array ( [id] => 14877123 [patent_doc_number] => 20190288803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-19 [patent_title] => APPARATUS AND METHOD FOR AVOIDING DETERMINISTIC BLANKING OF SECURE TRAFFIC [patent_app_type] => utility [patent_app_number] => 15/924219 [patent_app_country] => US [patent_app_date] => 2018-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4209 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15924219 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/924219
Apparatus and method for avoiding deterministic blanking of secure traffic Mar 17, 2018 Issued
Array ( [id] => 13436951 [patent_doc_number] => 20180270018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => REPETITION SCHEME FOR FLEXIBLE BANDWIDTH UTILIZATION [patent_app_type] => utility [patent_app_number] => 15/922719 [patent_app_country] => US [patent_app_date] => 2018-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7471 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15922719 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/922719
Repetition scheme for flexible bandwidth utilization Mar 14, 2018 Issued
Array ( [id] => 15141045 [patent_doc_number] => 10484021 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-11-19 [patent_title] => Log-likelihood ratio processing for linear block code decoding [patent_app_type] => utility [patent_app_number] => 15/916090 [patent_app_country] => US [patent_app_date] => 2018-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 12065 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15916090 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/916090
Log-likelihood ratio processing for linear block code decoding Mar 7, 2018 Issued
Array ( [id] => 15287653 [patent_doc_number] => 10516504 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-24 [patent_title] => Two bit error calibration device for 256 bit transfer and the method for performing the same [patent_app_type] => utility [patent_app_number] => 15/915083 [patent_app_country] => US [patent_app_date] => 2018-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5520 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 586 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15915083 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/915083
Two bit error calibration device for 256 bit transfer and the method for performing the same Mar 7, 2018 Issued
Array ( [id] => 14840509 [patent_doc_number] => 20190278655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-12 [patent_title] => PROVIDING DATA OF A MEMORY SYSTEM BASED ON AN ADJUSTABLE ERROR RATE [patent_app_type] => utility [patent_app_number] => 15/914402 [patent_app_country] => US [patent_app_date] => 2018-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7758 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15914402 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/914402
Providing data of a memory system based on an adjustable error rate Mar 6, 2018 Issued
Array ( [id] => 14645455 [patent_doc_number] => 10367481 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-30 [patent_title] => Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal feature [patent_app_type] => utility [patent_app_number] => 15/899497 [patent_app_country] => US [patent_app_date] => 2018-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3208 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 410 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15899497 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/899497
Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal feature Feb 19, 2018 Issued
Array ( [id] => 15137009 [patent_doc_number] => 10481972 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-11-19 [patent_title] => File verification using cyclic redundancy check [patent_app_type] => utility [patent_app_number] => 15/895718 [patent_app_country] => US [patent_app_date] => 2018-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5006 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15895718 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/895718
File verification using cyclic redundancy check Feb 12, 2018 Issued
Array ( [id] => 14206683 [patent_doc_number] => 10270474 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-04-23 [patent_title] => Partial concatenated coding system using algebraic code and LDPC code [patent_app_type] => utility [patent_app_number] => 15/890432 [patent_app_country] => US [patent_app_date] => 2018-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4155 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 344 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15890432 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/890432
Partial concatenated coding system using algebraic code and LDPC code Feb 6, 2018 Issued
Array ( [id] => 13350911 [patent_doc_number] => 20180226995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-09 [patent_title] => Polar Code Interleaving and Bit Selection [patent_app_type] => utility [patent_app_number] => 15/889204 [patent_app_country] => US [patent_app_date] => 2018-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4759 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15889204 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/889204
Polar code interleaving and bit selection Feb 5, 2018 Issued
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