Search

Kyle Vallecillo

Examiner (ID: 13968, Phone: (571)272-7716 , Office: P/2112 )

Most Active Art Unit
2112
Art Unit(s)
2112
Total Applications
757
Issued Applications
658
Pending Applications
0
Abandoned Applications
103

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17581190 [patent_doc_number] => 20220138045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => MEMORY DEVICE AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/398158 [patent_app_country] => US [patent_app_date] => 2021-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13370 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17398158 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/398158
Memory device and memory system Aug 9, 2021 Issued
Array ( [id] => 17247874 [patent_doc_number] => 20210367619 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => ERROR DETECTION [patent_app_type] => utility [patent_app_number] => 17/394118 [patent_app_country] => US [patent_app_date] => 2021-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9655 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17394118 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/394118
Error detection Aug 3, 2021 Issued
Array ( [id] => 18181812 [patent_doc_number] => 20230042541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => ATPG TESTING METHOD FOR LATCH BASED MEMORIES, FOR AREA REDUCTION [patent_app_type] => utility [patent_app_number] => 17/443556 [patent_app_country] => US [patent_app_date] => 2021-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9263 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17443556 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/443556
ATPG testing method for latch based memories, for area reduction Jul 26, 2021 Issued
Array ( [id] => 17879212 [patent_doc_number] => 11451247 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-20 [patent_title] => Decoding signals by guessing noise [patent_app_type] => utility [patent_app_number] => 17/371925 [patent_app_country] => US [patent_app_date] => 2021-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10442 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17371925 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/371925
Decoding signals by guessing noise Jul 8, 2021 Issued
Array ( [id] => 18104259 [patent_doc_number] => 11544145 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => Error coalescing [patent_app_type] => utility [patent_app_number] => 17/363622 [patent_app_country] => US [patent_app_date] => 2021-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7916 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17363622 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/363622
Error coalescing Jun 29, 2021 Issued
Array ( [id] => 17263970 [patent_doc_number] => 20210376955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => Checksum-Filtered Decoding, Checksum-Aided Forward Error Correction of Data Packets, Forward Error Correction of Data using Bit Erasure Channels and Sub-symbol Level Decoding for Erroneous Fountain codes [patent_app_type] => utility [patent_app_number] => 17/361526 [patent_app_country] => US [patent_app_date] => 2021-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 36396 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17361526 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/361526
Checksum-aided forward error correction of data packets Jun 28, 2021 Issued
Array ( [id] => 17171788 [patent_doc_number] => 20210325458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => ASYNCHRONOUS CIRCUITS AND TEST METHODS [patent_app_type] => utility [patent_app_number] => 17/359315 [patent_app_country] => US [patent_app_date] => 2021-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10727 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17359315 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/359315
Asynchronous circuits and test methods Jun 24, 2021 Issued
Array ( [id] => 18430443 [patent_doc_number] => 11675662 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => Extended error detection for a memory device [patent_app_type] => utility [patent_app_number] => 17/348211 [patent_app_country] => US [patent_app_date] => 2021-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 25034 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17348211 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/348211
Extended error detection for a memory device Jun 14, 2021 Issued
Array ( [id] => 17659279 [patent_doc_number] => 20220179744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => STORAGE DEVICE AND COMPUTING SYSTEM [patent_app_type] => utility [patent_app_number] => 17/348462 [patent_app_country] => US [patent_app_date] => 2021-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14964 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17348462 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/348462
Storage device and computing system Jun 14, 2021 Issued
Array ( [id] => 17128622 [patent_doc_number] => 20210303391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/347328 [patent_app_country] => US [patent_app_date] => 2021-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11189 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17347328 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/347328
Semiconductor devices Jun 13, 2021 Issued
Array ( [id] => 17751521 [patent_doc_number] => 20220229726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => ERROR CORRECTION OF MEMORY [patent_app_type] => utility [patent_app_number] => 17/326889 [patent_app_country] => US [patent_app_date] => 2021-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6118 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17326889 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/326889
Error correction of memory May 20, 2021 Issued
Array ( [id] => 17535430 [patent_doc_number] => 20220114039 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => DATA INTERPRETATION WITH MODULATION ERROR RATIO ANALYSIS [patent_app_type] => utility [patent_app_number] => 17/319903 [patent_app_country] => US [patent_app_date] => 2021-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10247 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17319903 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/319903
Data interpretation with modulation error ratio analysis May 12, 2021 Issued
Array ( [id] => 17372185 [patent_doc_number] => 20220027237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => METHOD FOR THE SECURED STORING OF A DATA ELEMENT IN AN EXTERNAL MEMORY AND INTERFACE MODULE [patent_app_type] => utility [patent_app_number] => 17/317353 [patent_app_country] => US [patent_app_date] => 2021-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4048 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17317353 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/317353
Method for the secured storing of a data element in an external memory and interface module May 10, 2021 Issued
Array ( [id] => 18206093 [patent_doc_number] => 11588504 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-21 [patent_title] => Rate matching methods for LDPC codes [patent_app_type] => utility [patent_app_number] => 17/314267 [patent_app_country] => US [patent_app_date] => 2021-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12201 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17314267 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/314267
Rate matching methods for LDPC codes May 6, 2021 Issued
Array ( [id] => 18121330 [patent_doc_number] => 11552733 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Apparatus and method for transmitting and receiving data in communication system [patent_app_type] => utility [patent_app_number] => 17/306246 [patent_app_country] => US [patent_app_date] => 2021-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5720 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17306246 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/306246
Apparatus and method for transmitting and receiving data in communication system May 2, 2021 Issued
Array ( [id] => 17024165 [patent_doc_number] => 20210248036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => FLASH MEMORY APPARATUS AND STORAGE MANAGEMENT METHOD FOR FLASH MEMORY [patent_app_type] => utility [patent_app_number] => 17/242326 [patent_app_country] => US [patent_app_date] => 2021-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16791 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17242326 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/242326
Flash memory apparatus and storage management method for flash memory Apr 27, 2021 Issued
Array ( [id] => 17892239 [patent_doc_number] => 11455210 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-09-27 [patent_title] => Error detection and correction in memory [patent_app_type] => utility [patent_app_number] => 17/239864 [patent_app_country] => US [patent_app_date] => 2021-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7651 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17239864 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/239864
Error detection and correction in memory Apr 25, 2021 Issued
Array ( [id] => 17893768 [patent_doc_number] => 11456758 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-09-27 [patent_title] => Adaptive soft-bit compression in flash memory [patent_app_type] => utility [patent_app_number] => 17/239057 [patent_app_country] => US [patent_app_date] => 2021-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6827 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17239057 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/239057
Adaptive soft-bit compression in flash memory Apr 22, 2021 Issued
Array ( [id] => 17038850 [patent_doc_number] => 20210255809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-19 [patent_title] => CONTROLLER, MEMORY SYSTEM, AND OPERATING METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 17/235252 [patent_app_country] => US [patent_app_date] => 2021-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6882 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17235252 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/235252
Controller, memory system, and operating methods thereof Apr 19, 2021 Issued
Array ( [id] => 17918752 [patent_doc_number] => 20220321148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => DYNAMIC BIT FLIPPING ORDER FOR ITERATIVE ERROR CORRECTION [patent_app_type] => utility [patent_app_number] => 17/223910 [patent_app_country] => US [patent_app_date] => 2021-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7865 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17223910 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/223910
Dynamic bit flipping order for iterative error correction Apr 5, 2021 Issued
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