
Kyle Walraed-sullivan
Examiner (ID: 701)
| Most Active Art Unit | 3635 |
| Art Unit(s) | 3635 |
| Total Applications | 1059 |
| Issued Applications | 711 |
| Pending Applications | 121 |
| Abandoned Applications | 247 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3087423
[patent_doc_number] => 05298117
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-03-29
[patent_title] => 'Etching of copper-containing devices'
[patent_app_type] => 1
[patent_app_number] => 8/094650
[patent_app_country] => US
[patent_app_date] => 1993-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 6
[patent_no_of_words] => 1967
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/298/05298117.pdf
[firstpage_image] =>[orig_patent_app_number] => 094650
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/094650 | Etching of copper-containing devices | Jul 18, 1993 | Issued |
Array
(
[id] => 3043551
[patent_doc_number] => 05286677
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-02-15
[patent_title] => 'Method for etching improved contact openings to peripheral circuit regions of a dram integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 8/057884
[patent_app_country] => US
[patent_app_date] => 1993-05-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 3481
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 203
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/286/05286677.pdf
[firstpage_image] =>[orig_patent_app_number] => 057884
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/057884 | Method for etching improved contact openings to peripheral circuit regions of a dram integrated circuit | May 6, 1993 | Issued |
Array
(
[id] => 3091077
[patent_doc_number] => 05312773
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-05-17
[patent_title] => 'Method of forming multilayer interconnection structure'
[patent_app_type] => 1
[patent_app_number] => 8/037640
[patent_app_country] => US
[patent_app_date] => 1993-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 2964
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 283
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/312/05312773.pdf
[firstpage_image] =>[orig_patent_app_number] => 037640
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/037640 | Method of forming multilayer interconnection structure | Mar 25, 1993 | Issued |
Array
(
[id] => 3011409
[patent_doc_number] => 05302233
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-04-12
[patent_title] => 'Method for shaping features of a semiconductor structure using chemical mechanical planarization (CMP)'
[patent_app_type] => 1
[patent_app_number] => 8/034421
[patent_app_country] => US
[patent_app_date] => 1993-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 9
[patent_no_of_words] => 3535
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/302/05302233.pdf
[firstpage_image] =>[orig_patent_app_number] => 034421
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/034421 | Method for shaping features of a semiconductor structure using chemical mechanical planarization (CMP) | Mar 18, 1993 | Issued |
Array
(
[id] => 2985445
[patent_doc_number] => 05266523
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-11-30
[patent_title] => 'Method of forming self-aligned contacts using the local oxidation of silicon'
[patent_app_type] => 1
[patent_app_number] => 8/031425
[patent_app_country] => US
[patent_app_date] => 1993-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 13
[patent_no_of_words] => 2608
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/266/05266523.pdf
[firstpage_image] =>[orig_patent_app_number] => 031425
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/031425 | Method of forming self-aligned contacts using the local oxidation of silicon | Mar 11, 1993 | Issued |
Array
(
[id] => 3083530
[patent_doc_number] => 05279990
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-01-18
[patent_title] => 'Method of making a small geometry contact using sidewall spacers'
[patent_app_type] => 1
[patent_app_number] => 8/031085
[patent_app_country] => US
[patent_app_date] => 1993-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 2769
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 299
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/279/05279990.pdf
[firstpage_image] =>[orig_patent_app_number] => 031085
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/031085 | Method of making a small geometry contact using sidewall spacers | Mar 11, 1993 | Issued |
| 08/023142 | METHOD FOR FORMING MULTILAYER INDIUM BUMP CONTACTS | Feb 23, 1993 | Abandoned |
Array
(
[id] => 3026687
[patent_doc_number] => 05328553
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-07-12
[patent_title] => 'Method for fabricating a semiconductor device having a planar surface'
[patent_app_type] => 1
[patent_app_number] => 8/012177
[patent_app_country] => US
[patent_app_date] => 1993-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 7
[patent_no_of_words] => 3081
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/328/05328553.pdf
[firstpage_image] =>[orig_patent_app_number] => 012177
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/012177 | Method for fabricating a semiconductor device having a planar surface | Feb 1, 1993 | Issued |
Array
(
[id] => 3075905
[patent_doc_number] => 05322816
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-06-21
[patent_title] => 'Method for forming deep conductive feedthroughs'
[patent_app_type] => 1
[patent_app_number] => 8/006215
[patent_app_country] => US
[patent_app_date] => 1993-01-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 2387
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 280
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/322/05322816.pdf
[firstpage_image] =>[orig_patent_app_number] => 006215
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/006215 | Method for forming deep conductive feedthroughs | Jan 18, 1993 | Issued |
Array
(
[id] => 3006157
[patent_doc_number] => 05308415
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-05-03
[patent_title] => 'Enhancing step coverage by creating a tapered profile through three dimensional resist pull back'
[patent_app_type] => 1
[patent_app_number] => 7/999404
[patent_app_country] => US
[patent_app_date] => 1992-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 14
[patent_no_of_words] => 2251
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/308/05308415.pdf
[firstpage_image] =>[orig_patent_app_number] => 999404
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/999404 | Enhancing step coverage by creating a tapered profile through three dimensional resist pull back | Dec 30, 1992 | Issued |
Array
(
[id] => 3090344
[patent_doc_number] => 05318663
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-06-07
[patent_title] => 'Method for thinning SOI films having improved thickness uniformity'
[patent_app_type] => 1
[patent_app_number] => 7/996209
[patent_app_country] => US
[patent_app_date] => 1992-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 10
[patent_no_of_words] => 2253
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 329
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/318/05318663.pdf
[firstpage_image] =>[orig_patent_app_number] => 996209
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/996209 | Method for thinning SOI films having improved thickness uniformity | Dec 22, 1992 | Issued |
Array
(
[id] => 2948461
[patent_doc_number] => 05262346
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-11-16
[patent_title] => 'Nitride polish stop for forming SOI wafers'
[patent_app_type] => 1
[patent_app_number] => 7/991222
[patent_app_country] => US
[patent_app_date] => 1992-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 8
[patent_no_of_words] => 2047
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 283
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/262/05262346.pdf
[firstpage_image] =>[orig_patent_app_number] => 991222
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/991222 | Nitride polish stop for forming SOI wafers | Dec 15, 1992 | Issued |
Array
(
[id] => 2976497
[patent_doc_number] => 05252517
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-10-12
[patent_title] => 'Method of conductor isolation from a conductive contact plug'
[patent_app_type] => 1
[patent_app_number] => 7/988626
[patent_app_country] => US
[patent_app_date] => 1992-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 2003
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/252/05252517.pdf
[firstpage_image] =>[orig_patent_app_number] => 988626
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/988626 | Method of conductor isolation from a conductive contact plug | Dec 9, 1992 | Issued |
Array
(
[id] => 3045697
[patent_doc_number] => 05304510
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-04-19
[patent_title] => 'Method of manufacturing a multilayered metallization structure in which the conductive layer and insulating layer are selectively deposited'
[patent_app_type] => 1
[patent_app_number] => 7/981427
[patent_app_country] => US
[patent_app_date] => 1992-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 42
[patent_no_of_words] => 8448
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/304/05304510.pdf
[firstpage_image] =>[orig_patent_app_number] => 981427
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/981427 | Method of manufacturing a multilayered metallization structure in which the conductive layer and insulating layer are selectively deposited | Nov 24, 1992 | Issued |
Array
(
[id] => 3028808
[patent_doc_number] => 05300188
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-04-05
[patent_title] => 'Process for making substantially smooth diamond'
[patent_app_type] => 1
[patent_app_number] => 7/975817
[patent_app_country] => US
[patent_app_date] => 1992-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 13
[patent_no_of_words] => 2847
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/300/05300188.pdf
[firstpage_image] =>[orig_patent_app_number] => 975817
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/975817 | Process for making substantially smooth diamond | Nov 12, 1992 | Issued |
Array
(
[id] => 2961245
[patent_doc_number] => 05264387
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-11-23
[patent_title] => 'Method of forming uniformly thin, isolated silicon mesas on an insulating substrate'
[patent_app_type] => 1
[patent_app_number] => 7/966959
[patent_app_country] => US
[patent_app_date] => 1992-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 3066
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/264/05264387.pdf
[firstpage_image] =>[orig_patent_app_number] => 966959
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/966959 | Method of forming uniformly thin, isolated silicon mesas on an insulating substrate | Oct 26, 1992 | Issued |
| 07/964587 | SELECTIVE PLANARIZATION METHOD AND APPARATUS | Oct 20, 1992 | Abandoned |
Array
(
[id] => 2968412
[patent_doc_number] => 05256248
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-10-26
[patent_title] => 'Method for patterning semiconductor'
[patent_app_type] => 1
[patent_app_number] => 7/959852
[patent_app_country] => US
[patent_app_date] => 1992-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 10
[patent_no_of_words] => 1175
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 287
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/256/05256248.pdf
[firstpage_image] =>[orig_patent_app_number] => 959852
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/959852 | Method for patterning semiconductor | Oct 12, 1992 | Issued |
Array
(
[id] => 2887527
[patent_doc_number] => 05238872
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-08-24
[patent_title] => 'Barrier metal contact architecture'
[patent_app_type] => 1
[patent_app_number] => 7/956455
[patent_app_country] => US
[patent_app_date] => 1992-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 3064
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 210
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/238/05238872.pdf
[firstpage_image] =>[orig_patent_app_number] => 956455
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/956455 | Barrier metal contact architecture | Oct 1, 1992 | Issued |
Array
(
[id] => 3043570
[patent_doc_number] => 05286678
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-02-15
[patent_title] => 'Single step salicidation process'
[patent_app_type] => 1
[patent_app_number] => 7/951945
[patent_app_country] => US
[patent_app_date] => 1992-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 21
[patent_no_of_words] => 4142
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/286/05286678.pdf
[firstpage_image] =>[orig_patent_app_number] => 951945
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/951945 | Single step salicidation process | Sep 27, 1992 | Issued |