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Kyle Walraed-sullivan

Examiner (ID: 701)

Most Active Art Unit
3635
Art Unit(s)
3635
Total Applications
1059
Issued Applications
711
Pending Applications
121
Abandoned Applications
247

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2595299 [patent_doc_number] => 04923822 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-05-08 [patent_title] => 'Method of fabricating a semiconductor device by capping a conductive layer with a nitride layer' [patent_app_type] => 1 [patent_app_number] => 7/356021 [patent_app_country] => US [patent_app_date] => 1989-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2444 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/923/04923822.pdf [firstpage_image] =>[orig_patent_app_number] => 356021 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/356021
Method of fabricating a semiconductor device by capping a conductive layer with a nitride layer May 21, 1989 Issued
Array ( [id] => 2693797 [patent_doc_number] => 05019531 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-05-28 [patent_title] => 'Process for selectively growing thin metallic film of copper or gold' [patent_app_type] => 1 [patent_app_number] => 7/354158 [patent_app_country] => US [patent_app_date] => 1989-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 6718 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/019/05019531.pdf [firstpage_image] =>[orig_patent_app_number] => 354158 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/354158
Process for selectively growing thin metallic film of copper or gold May 18, 1989 Issued
Array ( [id] => 2734791 [patent_doc_number] => 05077238 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-31 [patent_title] => 'Method of manufacturing a semiconductor device with a planar interlayer insulating film' [patent_app_type] => 1 [patent_app_number] => 7/353892 [patent_app_country] => US [patent_app_date] => 1989-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 43 [patent_no_of_words] => 7192 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/077/05077238.pdf [firstpage_image] =>[orig_patent_app_number] => 353892 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/353892
Method of manufacturing a semiconductor device with a planar interlayer insulating film May 17, 1989 Issued
Array ( [id] => 2822931 [patent_doc_number] => 05094975 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-10 [patent_title] => 'Method of making microscopic multiprobes' [patent_app_type] => 1 [patent_app_number] => 7/352573 [patent_app_country] => US [patent_app_date] => 1989-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 1728 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/094/05094975.pdf [firstpage_image] =>[orig_patent_app_number] => 352573 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/352573
Method of making microscopic multiprobes May 15, 1989 Issued
Array ( [id] => 2656549 [patent_doc_number] => 04962060 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-10-09 [patent_title] => 'Making a high speed interconnect system with refractory non-dogbone contacts and an active electromigration suppression mechanism' [patent_app_type] => 1 [patent_app_number] => 7/346050 [patent_app_country] => US [patent_app_date] => 1989-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 6318 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/962/04962060.pdf [firstpage_image] =>[orig_patent_app_number] => 346050 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/346050
Making a high speed interconnect system with refractory non-dogbone contacts and an active electromigration suppression mechanism May 1, 1989 Issued
Array ( [id] => 2595353 [patent_doc_number] => 04923825 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-05-08 [patent_title] => 'Method of treating a semiconductor body' [patent_app_type] => 1 [patent_app_number] => 7/345747 [patent_app_country] => US [patent_app_date] => 1989-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 2030 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/923/04923825.pdf [firstpage_image] =>[orig_patent_app_number] => 345747 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/345747
Method of treating a semiconductor body Apr 30, 1989 Issued
07/333650 IMPURITY - INDUCED SEEDING OF POLYCRYSTALLINE SEMICONDUCTORS Apr 4, 1989 Abandoned
Array ( [id] => 2632285 [patent_doc_number] => 04952526 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-08-28 [patent_title] => 'Method for the fabrication of an alternation of layers of monocrystalline semiconducting material and layers of insulating material' [patent_app_type] => 1 [patent_app_number] => 7/333083 [patent_app_country] => US [patent_app_date] => 1989-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 51 [patent_no_of_words] => 8681 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/952/04952526.pdf [firstpage_image] =>[orig_patent_app_number] => 333083 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/333083
Method for the fabrication of an alternation of layers of monocrystalline semiconducting material and layers of insulating material Apr 3, 1989 Issued
Array ( [id] => 2632432 [patent_doc_number] => 04977104 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-12-11 [patent_title] => 'Method for producing a semiconductor device by filling hollows with thermally decomposed doped and undoped polysilicon' [patent_app_type] => 1 [patent_app_number] => 7/327538 [patent_app_country] => US [patent_app_date] => 1989-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 28 [patent_no_of_words] => 4468 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/977/04977104.pdf [firstpage_image] =>[orig_patent_app_number] => 327538 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/327538
Method for producing a semiconductor device by filling hollows with thermally decomposed doped and undoped polysilicon Mar 22, 1989 Issued
Array ( [id] => 2871488 [patent_doc_number] => 05091342 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-02-25 [patent_title] => 'Multilevel resist plated transfer layer process for fine line lithography' [patent_app_type] => 1 [patent_app_number] => 7/315351 [patent_app_country] => US [patent_app_date] => 1989-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 25 [patent_no_of_words] => 5022 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/091/05091342.pdf [firstpage_image] =>[orig_patent_app_number] => 315351 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/315351
Multilevel resist plated transfer layer process for fine line lithography Feb 23, 1989 Issued
Array ( [id] => 2742697 [patent_doc_number] => 05023204 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-06-11 [patent_title] => 'Method of manufacturing semiconductor device using silicone protective layer' [patent_app_type] => 1 [patent_app_number] => 7/298950 [patent_app_country] => US [patent_app_date] => 1989-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 2763 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/023/05023204.pdf [firstpage_image] =>[orig_patent_app_number] => 298950 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/298950
Method of manufacturing semiconductor device using silicone protective layer Jan 18, 1989 Issued
Array ( [id] => 2766380 [patent_doc_number] => 05063175 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-11-05 [patent_title] => 'Method for manufacturing a planar electrical interconnection utilizing isotropic deposition of conductive material' [patent_app_type] => 1 [patent_app_number] => 7/287582 [patent_app_country] => US [patent_app_date] => 1988-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 28 [patent_no_of_words] => 4863 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/063/05063175.pdf [firstpage_image] =>[orig_patent_app_number] => 287582 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/287582
Method for manufacturing a planar electrical interconnection utilizing isotropic deposition of conductive material Dec 15, 1988 Issued
07/278088 METHOD FOR SELECTIVELY DEPOSITING REFRACTORY METAL ON SEMICONDUCTOR SUBSTRATES Nov 29, 1988 Abandoned
07/275755 METHOD FOR FORMING A FINE PATTERN BY USING A PATTERNED RESIST LAYER Nov 22, 1988 Abandoned
Array ( [id] => 2623724 [patent_doc_number] => 04956307 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-09-11 [patent_title] => 'Thin oxide sidewall insulators for silicon-over-insulator transistors' [patent_app_type] => 1 [patent_app_number] => 7/269803 [patent_app_country] => US [patent_app_date] => 1988-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 12 [patent_no_of_words] => 3106 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/956/04956307.pdf [firstpage_image] =>[orig_patent_app_number] => 269803 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/269803
Thin oxide sidewall insulators for silicon-over-insulator transistors Nov 9, 1988 Issued
07/225494 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE Jul 27, 1988 Abandoned
Array ( [id] => 2636450 [patent_doc_number] => 04914057 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-04-03 [patent_title] => 'Contacting method and structure for integrated circuit pads' [patent_app_type] => 1 [patent_app_number] => 7/323604 [patent_app_country] => US [patent_app_date] => 1988-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1805 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/914/04914057.pdf [firstpage_image] =>[orig_patent_app_number] => 323604 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/323604
Contacting method and structure for integrated circuit pads Jul 14, 1988 Issued
Array ( [id] => 2705314 [patent_doc_number] => 05001083 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-03-19 [patent_title] => 'Method of priming semiconductor substrate for subsequent photoresist masking and etching' [patent_app_type] => 1 [patent_app_number] => 7/217636 [patent_app_country] => US [patent_app_date] => 1988-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 1962 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/001/05001083.pdf [firstpage_image] =>[orig_patent_app_number] => 217636 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/217636
Method of priming semiconductor substrate for subsequent photoresist masking and etching Jul 11, 1988 Issued
Array ( [id] => 2584804 [patent_doc_number] => 04925809 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-05-15 [patent_title] => 'Semiconductor wafer and epitaxial growth on the semiconductor wafer with autodoping control and manufacturing method therefor' [patent_app_type] => 1 [patent_app_number] => 7/214501 [patent_app_country] => US [patent_app_date] => 1988-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 2740 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/925/04925809.pdf [firstpage_image] =>[orig_patent_app_number] => 214501 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/214501
Semiconductor wafer and epitaxial growth on the semiconductor wafer with autodoping control and manufacturing method therefor Jun 30, 1988 Issued
Array ( [id] => 2632214 [patent_doc_number] => 04952522 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-08-28 [patent_title] => 'Method of fabricating complementary semiconductor integrated circuits devices having an increased immunity to latch-up' [patent_app_type] => 1 [patent_app_number] => 7/213102 [patent_app_country] => US [patent_app_date] => 1988-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 4653 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 431 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/952/04952522.pdf [firstpage_image] =>[orig_patent_app_number] => 213102 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/213102
Method of fabricating complementary semiconductor integrated circuits devices having an increased immunity to latch-up Jun 27, 1988 Issued
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