Kyle Walraed-sullivan

Array ( [id] => 2854862 [patent_doc_number] => 05166093 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-24 [patent_title] => 'Method to reduce the reflectivity of a semi-conductor metallic surface' [patent_app_type] => 1 [patent_app_number] => 7/738530 [patent_app_country] => US [patent_app_date] => 1991-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2507 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/166/05166093.pdf [firstpage_image] =>[orig_patent_app_number] => 738530 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2817126 [patent_doc_number] => 05169491 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-08 [patent_title] => 'Method of etching SiO.sub.2 dielectric layers using chemical mechanical polishing techniques' [patent_app_type] => 1 [patent_app_number] => 7/737376 [patent_app_country] => US [patent_app_date] => 1991-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1539 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/169/05169491.pdf [firstpage_image] =>[orig_patent_app_number] => 737376 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2845982 [patent_doc_number] => 05110759 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-05 [patent_title] => 'Conductive plug forming method using laser planarization' [patent_app_type] => 1 [patent_app_number] => 7/737910 [patent_app_country] => US [patent_app_date] => 1991-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 22 [patent_no_of_words] => 5703 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/110/05110759.pdf [firstpage_image] =>[orig_patent_app_number] => 737910 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2793256 [patent_doc_number] => 05143865 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-01 [patent_title] => 'Metal bump type semiconductor device and method for manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 7/731392 [patent_app_country] => US [patent_app_date] => 1991-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 5873 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/143/05143865.pdf [firstpage_image] =>[orig_patent_app_number] => 731392 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2840277 [patent_doc_number] => 05137845 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-11 [patent_title] => 'Method of forming metal contact pads and terminals on semiconductor chips' [patent_app_type] => 1 [patent_app_number] => 7/729506 [patent_app_country] => US [patent_app_date] => 1991-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 19 [patent_no_of_words] => 3636 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/137/05137845.pdf [firstpage_image] =>[orig_patent_app_number] => 729506 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2671671 [patent_doc_number] => 05073518 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-17 [patent_title] => 'Process to mechanically and plastically deform solid ductile metal to fill contacts of conductive channels with ductile metal and process for dry polishing excess metal from a semiconductor wafer' [patent_app_type] => 1 [patent_app_number] => 7/718206 [patent_app_country] => US [patent_app_date] => 1991-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 3210 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/073/05073518.pdf [firstpage_image] =>[orig_patent_app_number] => 718206 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2945763 [patent_doc_number] => 05242507 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-07 [patent_title] => 'Impurity-induced seeding of polycrystalline semiconductors' [patent_app_type] => 1 [patent_app_number] => 7/700333 [patent_app_country] => US [patent_app_date] => 1991-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 20 [patent_no_of_words] => 2817 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/242/05242507.pdf [firstpage_image] =>[orig_patent_app_number] => 700333 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2877854 [patent_doc_number] => 05185296 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-02-09 [patent_title] => 'Method for forming a dielectric thin film or its pattern of high accuracy on a substrate' [patent_app_type] => 1 [patent_app_number] => 7/689730 [patent_app_country] => US [patent_app_date] => 1991-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 5204 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/185/05185296.pdf [firstpage_image] =>[orig_patent_app_number] => 689730 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2890712 [patent_doc_number] => 05270254 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-14 [patent_title] => 'Integrated circuit metallization with zero contact enclosure requirements and method of making the same' [patent_app_type] => 1 [patent_app_number] => 7/676084 [patent_app_country] => US [patent_app_date] => 1991-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 6555 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/270/05270254.pdf [firstpage_image] =>[orig_patent_app_number] => 676084 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2829583 [patent_doc_number] => 05175124 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-29 [patent_title] => 'Process for fabricating a semiconductor device using re-ionized rinse water' [patent_app_type] => 1 [patent_app_number] => 7/674000 [patent_app_country] => US [patent_app_date] => 1991-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2907 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/175/05175124.pdf [firstpage_image] =>[orig_patent_app_number] => 674000 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2812403 [patent_doc_number] => 05086017 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-02-04 [patent_title] => 'Self aligned silicide process for gate/runner without extra masking' [patent_app_type] => 1 [patent_app_number] => 7/672916 [patent_app_country] => US [patent_app_date] => 1991-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3368 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/086/05086017.pdf [firstpage_image] =>[orig_patent_app_number] => 672916 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2782295 [patent_doc_number] => 05164332 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-17 [patent_title] => 'Diffusion barrier for copper features' [patent_app_type] => 1 [patent_app_number] => 7/669814 [patent_app_country] => US [patent_app_date] => 1991-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1788 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/164/05164332.pdf [firstpage_image] =>[orig_patent_app_number] => 669814 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2857104 [patent_doc_number] => 05084403 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-01-28 [patent_title] => 'Method of manufacturing a semiconductor device including connecting a monocrystalline aluminum wire' [patent_app_type] => 1 [patent_app_number] => 7/668830 [patent_app_country] => US [patent_app_date] => 1991-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 1785 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/084/05084403.pdf [firstpage_image] =>[orig_patent_app_number] => 668830 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2803748 [patent_doc_number] => 05114872 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-19 [patent_title] => 'Forming planar ITO gate electrode array structures' [patent_app_type] => 1 [patent_app_number] => 7/663996 [patent_app_country] => US [patent_app_date] => 1991-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 1622 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/114/05114872.pdf [firstpage_image] =>[orig_patent_app_number] => 663996 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2793294 [patent_doc_number] => 05143867 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-01 [patent_title] => 'Method for depositing interconnection metallurgy using low temperature alloy processes' [patent_app_type] => 1 [patent_app_number] => 7/654999 [patent_app_country] => US [patent_app_date] => 1991-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 3119 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/143/05143867.pdf [firstpage_image] =>[orig_patent_app_number] => 654999 [rel_patent_id] =>[rel_patent_doc_number] =>)