Search

Kyle Zhai

Examiner (ID: 12523, Phone: (571)270-3740 , Office: P/2612 )

Most Active Art Unit
2612
Art Unit(s)
2679, 2612, 2677, 2628
Total Applications
472
Issued Applications
308
Pending Applications
49
Abandoned Applications
115

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4385827 [patent_doc_number] => 06303986 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Method of and apparatus for sealing an hermetic lid to a semiconductor die' [patent_app_type] => 1 [patent_app_number] => 9/124710 [patent_app_country] => US [patent_app_date] => 1998-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 5111 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/303/06303986.pdf [firstpage_image] =>[orig_patent_app_number] => 124710 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/124710
Method of and apparatus for sealing an hermetic lid to a semiconductor die Jul 28, 1998 Issued
Array ( [id] => 4366136 [patent_doc_number] => 06274442 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Transistor having a nitrogen incorporated epitaxially grown gate dielectric and method of making same' [patent_app_type] => 1 [patent_app_number] => 9/116417 [patent_app_country] => US [patent_app_date] => 1998-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3707 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/274/06274442.pdf [firstpage_image] =>[orig_patent_app_number] => 116417 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/116417
Transistor having a nitrogen incorporated epitaxially grown gate dielectric and method of making same Jul 14, 1998 Issued
09/103415 ELECTRONIC DEVICE HAVING FIBROUS INTERFACE Jun 23, 1998 Abandoned
Array ( [id] => 4172620 [patent_doc_number] => 06083804 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Method for fabricating a capacitor in a dynamic random access memory' [patent_app_type] => 1 [patent_app_number] => 9/103957 [patent_app_country] => US [patent_app_date] => 1998-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 1971 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 415 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/083/06083804.pdf [firstpage_image] =>[orig_patent_app_number] => 103957 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/103957
Method for fabricating a capacitor in a dynamic random access memory Jun 23, 1998 Issued
Array ( [id] => 4381636 [patent_doc_number] => 06261937 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Method for forming a semiconductor fuse' [patent_app_type] => 1 [patent_app_number] => 9/105107 [patent_app_country] => US [patent_app_date] => 1998-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2560 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/261/06261937.pdf [firstpage_image] =>[orig_patent_app_number] => 105107 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/105107
Method for forming a semiconductor fuse Jun 23, 1998 Issued
Array ( [id] => 4155461 [patent_doc_number] => 06156588 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Method of forming anti-fuse structure' [patent_app_type] => 1 [patent_app_number] => 9/102367 [patent_app_country] => US [patent_app_date] => 1998-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 2837 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/156/06156588.pdf [firstpage_image] =>[orig_patent_app_number] => 102367 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/102367
Method of forming anti-fuse structure Jun 22, 1998 Issued
Array ( [id] => 4395733 [patent_doc_number] => 06297170 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Sacrificial multilayer anti-reflective coating for mos gate formation' [patent_app_type] => 1 [patent_app_number] => 9/102797 [patent_app_country] => US [patent_app_date] => 1998-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 9074 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297170.pdf [firstpage_image] =>[orig_patent_app_number] => 102797 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/102797
Sacrificial multilayer anti-reflective coating for mos gate formation Jun 22, 1998 Issued
Array ( [id] => 4286800 [patent_doc_number] => 06268259 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Overhanging separator for self-defining stacked capacitor' [patent_app_type] => 1 [patent_app_number] => 9/103187 [patent_app_country] => US [patent_app_date] => 1998-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 19 [patent_no_of_words] => 1640 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/268/06268259.pdf [firstpage_image] =>[orig_patent_app_number] => 103187 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/103187
Overhanging separator for self-defining stacked capacitor Jun 22, 1998 Issued
Array ( [id] => 4250118 [patent_doc_number] => 06207530 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Dual gate FET and process' [patent_app_type] => 1 [patent_app_number] => 9/100900 [patent_app_country] => US [patent_app_date] => 1998-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3031 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/207/06207530.pdf [firstpage_image] =>[orig_patent_app_number] => 100900 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/100900
Dual gate FET and process Jun 18, 1998 Issued
Array ( [id] => 4293849 [patent_doc_number] => 06197657 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Method for producing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/095497 [patent_app_country] => US [patent_app_date] => 1998-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 3816 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/197/06197657.pdf [firstpage_image] =>[orig_patent_app_number] => 095497 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/095497
Method for producing a semiconductor device Jun 10, 1998 Issued
Array ( [id] => 4406131 [patent_doc_number] => 06171937 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Process for producing an MOS transistor' [patent_app_type] => 1 [patent_app_number] => 9/091150 [patent_app_country] => US [patent_app_date] => 1998-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 4122 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/171/06171937.pdf [firstpage_image] =>[orig_patent_app_number] => 091150 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/091150
Process for producing an MOS transistor Jun 8, 1998 Issued
Array ( [id] => 1463741 [patent_doc_number] => 06351034 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Clip chip carrier' [patent_app_type] => B1 [patent_app_number] => 09/088605 [patent_app_country] => US [patent_app_date] => 1998-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 4625 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/351/06351034.pdf [firstpage_image] =>[orig_patent_app_number] => 09088605 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/088605
Clip chip carrier May 31, 1998 Issued
09/081670 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE May 19, 1998 Abandoned
Array ( [id] => 4381113 [patent_doc_number] => 06261903 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Floating gate method and device' [patent_app_type] => 1 [patent_app_number] => 9/079140 [patent_app_country] => US [patent_app_date] => 1998-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5237 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/261/06261903.pdf [firstpage_image] =>[orig_patent_app_number] => 079140 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/079140
Floating gate method and device May 13, 1998 Issued
Array ( [id] => 4232303 [patent_doc_number] => 06117695 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Apparatus and method for testing a flip chip integrated circuit package adhesive layer' [patent_app_type] => 1 [patent_app_number] => 9/075300 [patent_app_country] => US [patent_app_date] => 1998-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 6281 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/117/06117695.pdf [firstpage_image] =>[orig_patent_app_number] => 075300 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/075300
Apparatus and method for testing a flip chip integrated circuit package adhesive layer May 7, 1998 Issued
Array ( [id] => 4183263 [patent_doc_number] => 06159817 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'Multi-tap thin film inductor' [patent_app_type] => 1 [patent_app_number] => 9/074185 [patent_app_country] => US [patent_app_date] => 1998-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1159 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/159/06159817.pdf [firstpage_image] =>[orig_patent_app_number] => 074185 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/074185
Multi-tap thin film inductor May 6, 1998 Issued
Array ( [id] => 4249194 [patent_doc_number] => 06207465 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Method of fabricating ferroelectric integrated circuit using dry and wet etching' [patent_app_type] => 1 [patent_app_number] => 9/062248 [patent_app_country] => US [patent_app_date] => 1998-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 7365 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/207/06207465.pdf [firstpage_image] =>[orig_patent_app_number] => 062248 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/062248
Method of fabricating ferroelectric integrated circuit using dry and wet etching Apr 16, 1998 Issued
Array ( [id] => 4064301 [patent_doc_number] => 06008118 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Method of fabricating a barrier layer' [patent_app_type] => 1 [patent_app_number] => 9/059310 [patent_app_country] => US [patent_app_date] => 1998-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1307 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/008/06008118.pdf [firstpage_image] =>[orig_patent_app_number] => 059310 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/059310
Method of fabricating a barrier layer Apr 12, 1998 Issued
Array ( [id] => 4301619 [patent_doc_number] => 06198159 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Bonded wafer, process for producing same and substrate' [patent_app_type] => 1 [patent_app_number] => 9/042697 [patent_app_country] => US [patent_app_date] => 1998-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 4788 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/198/06198159.pdf [firstpage_image] =>[orig_patent_app_number] => 042697 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/042697
Bonded wafer, process for producing same and substrate Mar 16, 1998 Issued
Array ( [id] => 4407331 [patent_doc_number] => 06238994 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Method of creating a rough electrode (high surface area) from Ti and TiN and resulting article' [patent_app_type] => 1 [patent_app_number] => 9/041917 [patent_app_country] => US [patent_app_date] => 1998-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 3503 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/238/06238994.pdf [firstpage_image] =>[orig_patent_app_number] => 041917 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/041917
Method of creating a rough electrode (high surface area) from Ti and TiN and resulting article Mar 12, 1998 Issued
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