Kyle Zhai
Examiner (ID: 12523, Phone: (571)270-3740 , Office: P/2612 )
Most Active Art Unit | 2612 |
Art Unit(s) | 2679, 2612, 2677, 2628 |
Total Applications | 472 |
Issued Applications | 308 |
Pending Applications | 49 |
Abandoned Applications | 115 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 4405036
[patent_doc_number] => 06271111
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-07
[patent_title] => 'High density pluggable connector array and process thereof'
[patent_app_type] => 1
[patent_app_number] => 9/030567
[patent_app_country] => US
[patent_app_date] => 1998-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 11
[patent_no_of_words] => 2852
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/271/06271111.pdf
[firstpage_image] =>[orig_patent_app_number] => 030567
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/030567 | High density pluggable connector array and process thereof | Feb 24, 1998 | Issued |
Array
(
[id] => 4381017
[patent_doc_number] => 06261896
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-17
[patent_title] => 'Memory device and method of forming the same'
[patent_app_type] => 1
[patent_app_number] => 9/030135
[patent_app_country] => US
[patent_app_date] => 1998-02-25
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/261/06261896.pdf
[firstpage_image] =>[orig_patent_app_number] => 030135
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/030135 | Memory device and method of forming the same | Feb 24, 1998 | Issued |
Array
(
[id] => 4084138
[patent_doc_number] => 06162703
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-19
[patent_title] => 'Packaging die preparation'
[patent_app_type] => 1
[patent_app_number] => 9/026999
[patent_app_country] => US
[patent_app_date] => 1998-02-23
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/162/06162703.pdf
[firstpage_image] =>[orig_patent_app_number] => 026999
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/026999 | Packaging die preparation | Feb 22, 1998 | Issued |
Array
(
[id] => 4300116
[patent_doc_number] => 06181000
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-30
[patent_title] => 'Lead frame for ball grid array, semiconductor device having it, and process for producing it'
[patent_app_type] => 1
[patent_app_number] => 9/028060
[patent_app_country] => US
[patent_app_date] => 1998-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 1575
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[pdf_file] => patents/06/181/06181000.pdf
[firstpage_image] =>[orig_patent_app_number] => 028060
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/028060 | Lead frame for ball grid array, semiconductor device having it, and process for producing it | Feb 22, 1998 | Issued |
Array
(
[id] => 4131491
[patent_doc_number] => 06146979
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-14
[patent_title] => 'Pressurized microbubble thin film separation process using a reusable substrate'
[patent_app_type] => 1
[patent_app_number] => 9/026032
[patent_app_country] => US
[patent_app_date] => 1998-02-19
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[pdf_file] => patents/06/146/06146979.pdf
[firstpage_image] =>[orig_patent_app_number] => 026032
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/026032 | Pressurized microbubble thin film separation process using a reusable substrate | Feb 18, 1998 | Issued |
Array
(
[id] => 4090762
[patent_doc_number] => 05966628
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-12
[patent_title] => 'Process design for wafer edge in vlsi'
[patent_app_type] => 1
[patent_app_number] => 9/023050
[patent_app_country] => US
[patent_app_date] => 1998-02-13
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[patent_no_of_words] => 2244
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[pdf_file] => patents/05/966/05966628.pdf
[firstpage_image] =>[orig_patent_app_number] => 023050
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/023050 | Process design for wafer edge in vlsi | Feb 12, 1998 | Issued |
Array
(
[id] => 4249358
[patent_doc_number] => 06207477
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-27
[patent_title] => 'Semiconductor device having a ball grid array and a fabrication process thereof'
[patent_app_type] => 1
[patent_app_number] => 9/021954
[patent_app_country] => US
[patent_app_date] => 1998-02-11
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[pdf_file] => patents/06/207/06207477.pdf
[firstpage_image] =>[orig_patent_app_number] => 021954
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/021954 | Semiconductor device having a ball grid array and a fabrication process thereof | Feb 10, 1998 | Issued |
Array
(
[id] => 4204914
[patent_doc_number] => 06077757
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-20
[patent_title] => 'Method of forming chip semiconductor devices'
[patent_app_type] => 1
[patent_app_number] => 9/020789
[patent_app_country] => US
[patent_app_date] => 1998-02-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[patent_no_of_words] => 3419
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[pdf_file] => patents/06/077/06077757.pdf
[firstpage_image] =>[orig_patent_app_number] => 020789
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/020789 | Method of forming chip semiconductor devices | Feb 8, 1998 | Issued |
Array
(
[id] => 4257648
[patent_doc_number] => 06208015
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-27
[patent_title] => 'Interlevel dielectric with air gaps to lessen capacitive coupling'
[patent_app_type] => 1
[patent_app_number] => 9/014192
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[patent_app_date] => 1998-01-27
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[pdf_file] => patents/06/208/06208015.pdf
[firstpage_image] =>[orig_patent_app_number] => 014192
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/014192 | Interlevel dielectric with air gaps to lessen capacitive coupling | Jan 26, 1998 | Issued |
Array
(
[id] => 4100316
[patent_doc_number] => 06066563
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-23
[patent_title] => 'Method for manufacturing semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 9/009879
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[pdf_file] => patents/06/066/06066563.pdf
[firstpage_image] =>[orig_patent_app_number] => 009879
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/009879 | Method for manufacturing semiconductor device | Jan 20, 1998 | Issued |
Array
(
[id] => 4187996
[patent_doc_number] => 06153456
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-28
[patent_title] => 'Method of selectively applying dopants to an integrated circuit semiconductor device without using a mask'
[patent_app_type] => 1
[patent_app_number] => 9/007117
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[patent_app_date] => 1998-01-14
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[pdf_file] => patents/06/153/06153456.pdf
[firstpage_image] =>[orig_patent_app_number] => 007117
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/007117 | Method of selectively applying dopants to an integrated circuit semiconductor device without using a mask | Jan 13, 1998 | Issued |
Array
(
[id] => 4125074
[patent_doc_number] => 06127240
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-03
[patent_title] => 'Method of manufacturing a semiconductor device having a capacitor'
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[patent_app_country] => US
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[pdf_file] => patents/06/127/06127240.pdf
[firstpage_image] =>[orig_patent_app_number] => 004280
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/004280 | Method of manufacturing a semiconductor device having a capacitor | Jan 7, 1998 | Issued |
Array
(
[id] => 4151599
[patent_doc_number] => 06124141
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[patent_issue_date] => 2000-09-26
[patent_title] => 'Non-destructive method and device for measuring the depth of a buried interface'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/004074 | Non-destructive method and device for measuring the depth of a buried interface | Jan 6, 1998 | Issued |
Array
(
[id] => 4249468
[patent_doc_number] => 06207485
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[patent_issue_date] => 2001-03-27
[patent_title] => 'Integration of high K spacers for dual gate oxide channel fabrication technique'
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[firstpage_image] =>[orig_patent_app_number] => 002725
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/002725 | Integration of high K spacers for dual gate oxide channel fabrication technique | Jan 4, 1998 | Issued |
Array
(
[id] => 1494943
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[patent_title] => 'Semiconductor devices having cooperative mode option at assembly stage and method thereof'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/001087 | Semiconductor devices having cooperative mode option at assembly stage and method thereof | Dec 29, 1997 | Issued |
Array
(
[id] => 4233619
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[patent_title] => 'Method of forming complementary type conductive regions on a substrate'
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[pdf_file] => patents/06/074/06074902.pdf
[firstpage_image] =>[orig_patent_app_number] => 996086
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/996086 | Method of forming complementary type conductive regions on a substrate | Dec 21, 1997 | Issued |
Array
(
[id] => 4394475
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[patent_issue_date] => 2001-10-02
[patent_title] => 'Method for manufacturing ferroelectric capacitor and method for manufacturing ferroelectric memory'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/988687 | Method for manufacturing ferroelectric capacitor and method for manufacturing ferroelectric memory | Dec 10, 1997 | Issued |
Array
(
[id] => 1354585
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Array
(
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Array
(
[id] => 1025135
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[pdf_file] => patents/RE/038/RE038727.pdf
[firstpage_image] =>[orig_patent_app_number] => 08999682
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/999682 | Photoelectric conversion device and method of making the same | Oct 7, 1997 | Issued |