Search

Kyle Zhai

Examiner (ID: 12523, Phone: (571)270-3740 , Office: P/2612 )

Most Active Art Unit
2612
Art Unit(s)
2679, 2612, 2677, 2628
Total Applications
472
Issued Applications
308
Pending Applications
49
Abandoned Applications
115

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1514541 [patent_doc_number] => 06420256 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-16 [patent_title] => 'Method of improving interconnect of semiconductor devices by using a flattened ball bond' [patent_app_type] => B1 [patent_app_number] => 09/684448 [patent_app_country] => US [patent_app_date] => 2000-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3297 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/420/06420256.pdf [firstpage_image] =>[orig_patent_app_number] => 09684448 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/684448
Method of improving interconnect of semiconductor devices by using a flattened ball bond Oct 5, 2000 Issued
Array ( [id] => 1297507 [patent_doc_number] => 06627532 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Method of decreasing the K value in SiOC layer deposited by chemical vapor deposition' [patent_app_type] => B1 [patent_app_number] => 09/679843 [patent_app_country] => US [patent_app_date] => 2000-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 9124 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/627/06627532.pdf [firstpage_image] =>[orig_patent_app_number] => 09679843 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/679843
Method of decreasing the K value in SiOC layer deposited by chemical vapor deposition Oct 4, 2000 Issued
Array ( [id] => 1440038 [patent_doc_number] => 06495419 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'Nonvolatile memory in CMOS process flow' [patent_app_type] => B1 [patent_app_number] => 09/670997 [patent_app_country] => US [patent_app_date] => 2000-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4192 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/495/06495419.pdf [firstpage_image] =>[orig_patent_app_number] => 09670997 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/670997
Nonvolatile memory in CMOS process flow Sep 26, 2000 Issued
Array ( [id] => 7634864 [patent_doc_number] => 06656754 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-02 [patent_title] => 'Method of forming a semiconductor chip carrier' [patent_app_type] => B1 [patent_app_number] => 09/652060 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 4660 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 14 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/656/06656754.pdf [firstpage_image] =>[orig_patent_app_number] => 09652060 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/652060
Method of forming a semiconductor chip carrier Aug 30, 2000 Issued
Array ( [id] => 4413586 [patent_doc_number] => 06300649 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility' [patent_app_type] => 1 [patent_app_number] => 9/632456 [patent_app_country] => US [patent_app_date] => 2000-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 3867 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/300/06300649.pdf [firstpage_image] =>[orig_patent_app_number] => 632456 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/632456
Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility Aug 3, 2000 Issued
09/605198 Method of and apparatus for sealing an hermetic lid to a semiconductor die Jun 26, 2000 Abandoned
Array ( [id] => 1418473 [patent_doc_number] => 06514853 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Semiconductor device and a manufacturing process therefor' [patent_app_type] => B1 [patent_app_number] => 09/592797 [patent_app_country] => US [patent_app_date] => 2000-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6072 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/514/06514853.pdf [firstpage_image] =>[orig_patent_app_number] => 09592797 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/592797
Semiconductor device and a manufacturing process therefor Jun 12, 2000 Issued
Array ( [id] => 1418121 [patent_doc_number] => 06514824 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Semiconductor device with a pair of transistors having dual work function gate electrodes' [patent_app_type] => B1 [patent_app_number] => 09/591108 [patent_app_country] => US [patent_app_date] => 2000-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 5155 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/514/06514824.pdf [firstpage_image] =>[orig_patent_app_number] => 09591108 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/591108
Semiconductor device with a pair of transistors having dual work function gate electrodes Jun 8, 2000 Issued
Array ( [id] => 4354312 [patent_doc_number] => 06200842 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Method of forming complementary type conductive regions on a substrate' [patent_app_type] => 1 [patent_app_number] => 9/547194 [patent_app_country] => US [patent_app_date] => 2000-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 2960 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/200/06200842.pdf [firstpage_image] =>[orig_patent_app_number] => 547194 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/547194
Method of forming complementary type conductive regions on a substrate Apr 10, 2000 Issued
Array ( [id] => 1361151 [patent_doc_number] => 06569699 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Two layer mirror for LCD-on-silicon products and method of fabrication thereof' [patent_app_type] => B1 [patent_app_number] => 09/495347 [patent_app_country] => US [patent_app_date] => 2000-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1901 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/569/06569699.pdf [firstpage_image] =>[orig_patent_app_number] => 09495347 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/495347
Two layer mirror for LCD-on-silicon products and method of fabrication thereof Jan 31, 2000 Issued
Array ( [id] => 1503754 [patent_doc_number] => 06465369 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Method for stabilizing semiconductor degas temperature' [patent_app_type] => B1 [patent_app_number] => 09/488847 [patent_app_country] => US [patent_app_date] => 2000-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1915 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/465/06465369.pdf [firstpage_image] =>[orig_patent_app_number] => 09488847 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/488847
Method for stabilizing semiconductor degas temperature Jan 20, 2000 Issued
Array ( [id] => 1415595 [patent_doc_number] => 06511903 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-28 [patent_title] => 'Method of depositing a low k dielectric with organo silane' [patent_app_type] => B1 [patent_app_number] => 09/465233 [patent_app_country] => US [patent_app_date] => 1999-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 29 [patent_no_of_words] => 8088 [patent_no_of_claims] => 61 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/511/06511903.pdf [firstpage_image] =>[orig_patent_app_number] => 09465233 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/465233
Method of depositing a low k dielectric with organo silane Dec 15, 1999 Issued
Array ( [id] => 4381510 [patent_doc_number] => 06294449 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Self-aligned contact for closely spaced transistors' [patent_app_type] => 1 [patent_app_number] => 9/447627 [patent_app_country] => US [patent_app_date] => 1999-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1711 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/294/06294449.pdf [firstpage_image] =>[orig_patent_app_number] => 447627 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/447627
Self-aligned contact for closely spaced transistors Nov 22, 1999 Issued
Array ( [id] => 1246618 [patent_doc_number] => 06677626 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-13 [patent_title] => 'Semiconductor device with alternating conductivity type layer and method of manufacturing the same' [patent_app_type] => B1 [patent_app_number] => 09/438077 [patent_app_country] => US [patent_app_date] => 1999-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4993 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/677/06677626.pdf [firstpage_image] =>[orig_patent_app_number] => 09438077 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/438077
Semiconductor device with alternating conductivity type layer and method of manufacturing the same Nov 9, 1999 Issued
Array ( [id] => 4414397 [patent_doc_number] => 06265773 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Vertically mountable and alignable semiconductor device, assembly, and methods' [patent_app_type] => 1 [patent_app_number] => 9/416357 [patent_app_country] => US [patent_app_date] => 1999-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 4711 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/265/06265773.pdf [firstpage_image] =>[orig_patent_app_number] => 416357 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/416357
Vertically mountable and alignable semiconductor device, assembly, and methods Oct 11, 1999 Issued
Array ( [id] => 4274941 [patent_doc_number] => 06307230 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Transistor having an improved sidewall gate structure and method of construction' [patent_app_type] => 1 [patent_app_number] => 9/416380 [patent_app_country] => US [patent_app_date] => 1999-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 3678 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/307/06307230.pdf [firstpage_image] =>[orig_patent_app_number] => 416380 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/416380
Transistor having an improved sidewall gate structure and method of construction Oct 11, 1999 Issued
Array ( [id] => 1458838 [patent_doc_number] => 06426278 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'Projection gas immersion laser dopant process (PGILD) fabrication of diffusion halos' [patent_app_type] => B1 [patent_app_number] => 09/413997 [patent_app_country] => US [patent_app_date] => 1999-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2846 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/426/06426278.pdf [firstpage_image] =>[orig_patent_app_number] => 09413997 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/413997
Projection gas immersion laser dopant process (PGILD) fabrication of diffusion halos Oct 6, 1999 Issued
Array ( [id] => 1559577 [patent_doc_number] => 06436723 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Etching method and etching apparatus method for manufacturing semiconductor device and semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/408177 [patent_app_country] => US [patent_app_date] => 1999-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 17 [patent_no_of_words] => 7302 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/436/06436723.pdf [firstpage_image] =>[orig_patent_app_number] => 09408177 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/408177
Etching method and etching apparatus method for manufacturing semiconductor device and semiconductor device Sep 28, 1999 Issued
Array ( [id] => 1490057 [patent_doc_number] => 06417021 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Method of fabricating a piezoresistive pressure sensor' [patent_app_type] => B1 [patent_app_number] => 09/404507 [patent_app_country] => US [patent_app_date] => 1999-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2575 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/417/06417021.pdf [firstpage_image] =>[orig_patent_app_number] => 09404507 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/404507
Method of fabricating a piezoresistive pressure sensor Sep 22, 1999 Issued
Array ( [id] => 4277466 [patent_doc_number] => 06246120 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Sidewalls for guiding the via etch' [patent_app_type] => 1 [patent_app_number] => 9/401964 [patent_app_country] => US [patent_app_date] => 1999-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 2855 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/246/06246120.pdf [firstpage_image] =>[orig_patent_app_number] => 401964 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/401964
Sidewalls for guiding the via etch Sep 21, 1999 Issued
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