
Lalrinfamkim Hmar Malsawma
Examiner (ID: 2370)
| Most Active Art Unit | 2892 |
| Art Unit(s) | 2823, 2892, 2825 |
| Total Applications | 1951 |
| Issued Applications | 1709 |
| Pending Applications | 105 |
| Abandoned Applications | 179 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 15688295
[patent_doc_number] => 20200098811
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-03-26
[patent_title] => CHIP PACKAGE AND METHOD FOR FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/581594
[patent_app_country] => US
[patent_app_date] => 2019-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7462
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -27
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16581594
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/581594 | Chip package with substrate having first opening surrounded by second opening and method for forming the same | Sep 23, 2019 | Issued |
Array
(
[id] => 17758109
[patent_doc_number] => 11398408
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-07-26
[patent_title] => Semiconductor substrate with trace connected to via at a level within a dielectric layer
[patent_app_type] => utility
[patent_app_number] => 16/581018
[patent_app_country] => US
[patent_app_date] => 2019-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 21
[patent_no_of_words] => 6651
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16581018
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/581018 | Semiconductor substrate with trace connected to via at a level within a dielectric layer | Sep 23, 2019 | Issued |
Array
(
[id] => 16944252
[patent_doc_number] => 11056503
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-07-06
[patent_title] => Semiconductor memory device including vertical barrier
[patent_app_type] => utility
[patent_app_number] => 16/580817
[patent_app_country] => US
[patent_app_date] => 2019-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 22
[patent_no_of_words] => 10110
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16580817
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/580817 | Semiconductor memory device including vertical barrier | Sep 23, 2019 | Issued |
Array
(
[id] => 16981748
[patent_doc_number] => 20210225985
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-22
[patent_title] => Wire Structure, Display Panel, Display Device and Manufacturing Method
[patent_app_type] => utility
[patent_app_number] => 16/756144
[patent_app_country] => US
[patent_app_date] => 2019-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5070
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 43
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16756144
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/756144 | Wire structure, display panel, display device with high thermal conductivity layer and manufacturing method | Sep 23, 2019 | Issued |
Array
(
[id] => 19123673
[patent_doc_number] => 11967668
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-04-23
[patent_title] => Optoelectronic component with conductive, flexible and extendable connecting element and method for producing the same
[patent_app_type] => utility
[patent_app_number] => 17/283493
[patent_app_country] => US
[patent_app_date] => 2019-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 4849
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17283493
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/283493 | Optoelectronic component with conductive, flexible and extendable connecting element and method for producing the same | Sep 23, 2019 | Issued |
Array
(
[id] => 16544953
[patent_doc_number] => 20200411368
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-12-31
[patent_title] => Semiconductor Device And Method For Manufacturing The Same
[patent_app_type] => utility
[patent_app_number] => 16/581010
[patent_app_country] => US
[patent_app_date] => 2019-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5438
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16581010
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/581010 | Semiconductor device having opening and via hole and method for manufacturing the same | Sep 23, 2019 | Issued |
Array
(
[id] => 15841173
[patent_doc_number] => 20200135869
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-30
[patent_title] => INTEGRATED CIRCUIT LAYOUTS WITH SOURCE AND DRAIN CONTACTS OF DIFFERENT WIDTHS
[patent_app_type] => utility
[patent_app_number] => 16/580779
[patent_app_country] => US
[patent_app_date] => 2019-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10675
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16580779
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/580779 | Integrated circuit layouts with source and drain contacts of different widths | Sep 23, 2019 | Issued |
Array
(
[id] => 16723895
[patent_doc_number] => 20210091042
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-25
[patent_title] => SEMICONDUCTOR DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/581009
[patent_app_country] => US
[patent_app_date] => 2019-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5673
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16581009
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/581009 | Semiconductor device package with stacked die having traces on lateral surface | Sep 23, 2019 | Issued |
Array
(
[id] => 16723869
[patent_doc_number] => 20210091016
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-25
[patent_title] => TRANSFORMERS WITH BUILD-UP FILMS
[patent_app_type] => utility
[patent_app_number] => 16/581033
[patent_app_country] => US
[patent_app_date] => 2019-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3761
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -26
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16581033
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/581033 | Transformers with build-up films | Sep 23, 2019 | Issued |
Array
(
[id] => 16724090
[patent_doc_number] => 20210091237
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-25
[patent_title] => SCHOTTKY DIODE
[patent_app_type] => utility
[patent_app_number] => 16/581044
[patent_app_country] => US
[patent_app_date] => 2019-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2113
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16581044
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/581044 | Low leakage Schottky diode | Sep 23, 2019 | Issued |
Array
(
[id] => 17493568
[patent_doc_number] => 11282885
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-03-22
[patent_title] => Wafer structure and chip structure having through-hole electrical connection for bonded chips
[patent_app_type] => utility
[patent_app_number] => 16/581093
[patent_app_country] => US
[patent_app_date] => 2019-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6831
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 246
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16581093
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/581093 | Wafer structure and chip structure having through-hole electrical connection for bonded chips | Sep 23, 2019 | Issued |
Array
(
[id] => 15718153
[patent_doc_number] => 20200105844
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-02
[patent_title] => OLED SUBSTRATE, MANUFACTURING METHOD THEREOF, TRANSPARENT DISPLAY
[patent_app_type] => utility
[patent_app_number] => 16/571570
[patent_app_country] => US
[patent_app_date] => 2019-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6347
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 44
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16571570
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/571570 | Transparent display with OLED substrate having multiple hollow parts and manufacturing method thereof | Sep 15, 2019 | Issued |
Array
(
[id] => 15352195
[patent_doc_number] => 20200013989
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-01-09
[patent_title] => DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/572462
[patent_app_country] => US
[patent_app_date] => 2019-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11810
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16572462
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/572462 | Display apparatus with substrate hole and touch electrode | Sep 15, 2019 | Issued |
Array
(
[id] => 16172771
[patent_doc_number] => 10714348
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-07-14
[patent_title] => Semiconductor device having hydrogen in a dielectric layer
[patent_app_type] => utility
[patent_app_number] => 16/568585
[patent_app_country] => US
[patent_app_date] => 2019-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 20
[patent_no_of_words] => 6530
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16568585
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/568585 | Semiconductor device having hydrogen in a dielectric layer | Sep 11, 2019 | Issued |
Array
(
[id] => 15370045
[patent_doc_number] => 20200020787
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-01-16
[patent_title] => REPLACEMENT METAL GATE STRUCTURES
[patent_app_type] => utility
[patent_app_number] => 16/568780
[patent_app_country] => US
[patent_app_date] => 2019-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3090
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16568780
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/568780 | Replacement metal gate structures | Sep 11, 2019 | Issued |
Array
(
[id] => 15841105
[patent_doc_number] => 20200135835
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-30
[patent_title] => DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/550919
[patent_app_country] => US
[patent_app_date] => 2019-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6871
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16550919
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/550919 | Display device having an encapsulation layer and power line in non-display area | Aug 25, 2019 | Issued |
Array
(
[id] => 18040333
[patent_doc_number] => 20220384550
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-01
[patent_title] => DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/957605
[patent_app_country] => US
[patent_app_date] => 2019-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17688
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16957605
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/957605 | Display device with transistors oriented in directions intersecting direction of driving transistor and manufacturing method thereof | Aug 22, 2019 | Issued |
Array
(
[id] => 15503267
[patent_doc_number] => 20200051822
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-02-13
[patent_title] => MODULE INCLUDING METALLIZED CERAMIC TUBES FOR RF AND GAS DELIVERY
[patent_app_type] => utility
[patent_app_number] => 16/546145
[patent_app_country] => US
[patent_app_date] => 2019-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4787
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => 0
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16546145
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/546145 | Apparatus including metallized-ceramic tubes for radio-frequency and gas delivery | Aug 19, 2019 | Issued |
Array
(
[id] => 16617215
[patent_doc_number] => 20210035868
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-02-04
[patent_title] => Semiconductor Device and Method of Manufacturing
[patent_app_type] => utility
[patent_app_number] => 16/527350
[patent_app_country] => US
[patent_app_date] => 2019-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9746
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16527350
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/527350 | Method of manufacturing semiconductor devices with multiple silicide regions | Jul 30, 2019 | Issued |
Array
(
[id] => 16210476
[patent_doc_number] => 20200243466
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-30
[patent_title] => SEMICONDUCTOR DEVICE HAVING BONDING PADS
[patent_app_type] => utility
[patent_app_number] => 16/527323
[patent_app_country] => US
[patent_app_date] => 2019-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6144
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16527323
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/527323 | Semiconductor device bonded by bonding pads | Jul 30, 2019 | Issued |