
Lalrinfamkim Hmar Malsawma
Examiner (ID: 14279)
| Most Active Art Unit | 2892 |
| Art Unit(s) | 2823, 2892, 2825 |
| Total Applications | 1954 |
| Issued Applications | 1715 |
| Pending Applications | 94 |
| Abandoned Applications | 179 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10073566
[patent_doc_number] => 09111931
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-08-18
[patent_title] => 'Method of forming an interconnect structure with high process margins'
[patent_app_type] => utility
[patent_app_number] => 14/161500
[patent_app_country] => US
[patent_app_date] => 2014-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 2670
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14161500
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/161500 | Method of forming an interconnect structure with high process margins | Jan 21, 2014 | Issued |
Array
(
[id] => 10519077
[patent_doc_number] => 09246134
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-01-26
[patent_title] => 'Lamination transfer films for forming articles with engineered voids'
[patent_app_type] => utility
[patent_app_number] => 14/159300
[patent_app_country] => US
[patent_app_date] => 2014-01-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 27
[patent_no_of_words] => 16066
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14159300
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/159300 | Lamination transfer films for forming articles with engineered voids | Jan 19, 2014 | Issued |
Array
(
[id] => 10322002
[patent_doc_number] => 20150207006
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-07-23
[patent_title] => 'SYSTEM AND METHOD FOR TRAPPING LIGHT IN A SOLAR CELL'
[patent_app_type] => utility
[patent_app_number] => 14/159002
[patent_app_country] => US
[patent_app_date] => 2014-01-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5884
[patent_no_of_claims] => 20
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14159002
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/159002 | SYSTEM AND METHOD FOR TRAPPING LIGHT IN A SOLAR CELL | Jan 19, 2014 | Abandoned |
Array
(
[id] => 10597393
[patent_doc_number] => 09318488
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-04-19
[patent_title] => 'Semiconductor device and formation thereof'
[patent_app_type] => utility
[patent_app_number] => 14/147851
[patent_app_country] => US
[patent_app_date] => 2014-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 5558
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14147851
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/147851 | Semiconductor device and formation thereof | Jan 5, 2014 | Issued |
Array
(
[id] => 10309382
[patent_doc_number] => 20150194382
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-07-09
[patent_title] => 'INTERCONNECT AND METHOD OF FABRICATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 14/146911
[patent_app_country] => US
[patent_app_date] => 2014-01-03
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/146911 | INTERCONNECT AND METHOD OF FABRICATING THE SAME | Jan 2, 2014 | Abandoned |
Array
(
[id] => 10053617
[patent_doc_number] => 09093503
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-07-28
[patent_title] => 'Semiconductor chip with a dual damascene wire and through-substrate via (TSV) structure'
[patent_app_type] => utility
[patent_app_number] => 14/146788
[patent_app_country] => US
[patent_app_date] => 2014-01-03
[patent_effective_date] => 0000-00-00
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14146788
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/146788 | Semiconductor chip with a dual damascene wire and through-substrate via (TSV) structure | Jan 2, 2014 | Issued |
Array
(
[id] => 10518941
[patent_doc_number] => 09245996
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-01-26
[patent_title] => 'Lateral double-diffused metal-oxide-semiconudctor transistor device and layout pattern for LDMOS transistor device'
[patent_app_type] => utility
[patent_app_number] => 14/146012
[patent_app_country] => US
[patent_app_date] => 2014-01-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 3701
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14146012
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/146012 | Lateral double-diffused metal-oxide-semiconudctor transistor device and layout pattern for LDMOS transistor device | Jan 1, 2014 | Issued |
Array
(
[id] => 10302896
[patent_doc_number] => 20150187896
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-07-02
[patent_title] => 'SILICIDE PROTECTION DURING CONTACT METALLIZATION AND RESULTING SEMICONDUCTOR STRUCTURES'
[patent_app_type] => utility
[patent_app_number] => 14/146399
[patent_app_country] => US
[patent_app_date] => 2014-01-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 8669
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14146399
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/146399 | Silicide protection during contact metallization and resulting semiconductor structures | Jan 1, 2014 | Issued |
Array
(
[id] => 10638608
[patent_doc_number] => 09356120
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-05-31
[patent_title] => 'Metal gate transistor and method for tuning metal gate profile'
[patent_app_type] => utility
[patent_app_number] => 14/145684
[patent_app_country] => US
[patent_app_date] => 2013-12-31
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/145684 | Metal gate transistor and method for tuning metal gate profile | Dec 30, 2013 | Issued |
Array
(
[id] => 10302874
[patent_doc_number] => 20150187874
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-07-02
[patent_title] => 'Field-Effect Semiconductor Device and Manufacturing Therefor'
[patent_app_type] => utility
[patent_app_number] => 14/145166
[patent_app_country] => US
[patent_app_date] => 2013-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/145166 | Field-effect semiconductor device and manufacturing therefor | Dec 30, 2013 | Issued |
Array
(
[id] => 10195884
[patent_doc_number] => 09224799
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[patent_kind] => B2
[patent_issue_date] => 2015-12-29
[patent_title] => 'Capacitors including inner and outer electrodes'
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[patent_app_number] => 14/145117
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/145117 | Capacitors including inner and outer electrodes | Dec 30, 2013 | Issued |
Array
(
[id] => 9710634
[patent_doc_number] => 08835202
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-09-16
[patent_title] => 'Structure and method for LED with phosphor coating'
[patent_app_type] => utility
[patent_app_number] => 14/140906
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/140906 | Structure and method for LED with phosphor coating | Dec 25, 2013 | Issued |
Array
(
[id] => 9627051
[patent_doc_number] => 08796734
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[patent_kind] => B2
[patent_issue_date] => 2014-08-05
[patent_title] => 'Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication'
[patent_app_type] => utility
[patent_app_number] => 14/104924
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/104924 | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication | Dec 11, 2013 | Issued |
Array
(
[id] => 10893347
[patent_doc_number] => 08916962
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[patent_kind] => B2
[patent_issue_date] => 2014-12-23
[patent_title] => 'III-nitride transistor with source-connected heat spreading plate'
[patent_app_type] => utility
[patent_app_number] => 14/101710
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/101710 | III-nitride transistor with source-connected heat spreading plate | Dec 9, 2013 | Issued |
Array
(
[id] => 10531506
[patent_doc_number] => 09257655
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-02-09
[patent_title] => 'Light-emitting element, light-emitting device, electronic device, and lighting device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/101623 | Light-emitting element, light-emitting device, electronic device, and lighting device | Dec 9, 2013 | Issued |
Array
(
[id] => 10138731
[patent_doc_number] => 09172054
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[patent_issue_date] => 2015-10-27
[patent_title] => 'Organic light emitting display device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/101605 | Organic light emitting display device | Dec 9, 2013 | Issued |
Array
(
[id] => 10079838
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[patent_title] => 'Low cost transistors'
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Array
(
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[patent_issue_date] => 2015-01-01
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 14/101654 | Light emitting module and lighting apparatus having the same | Dec 9, 2013 | Issued |