Search

Lalrinfamkim Hmar Malsawma

Examiner (ID: 15570)

Most Active Art Unit
2892
Art Unit(s)
2825, 2823, 2892
Total Applications
1945
Issued Applications
1698
Pending Applications
102
Abandoned Applications
180

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9515204 [patent_doc_number] => 20140151696 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-05 [patent_title] => 'DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/176242 [patent_app_country] => US [patent_app_date] => 2014-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 17722 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14176242 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/176242
Display device and method for manufacturing the same Feb 9, 2014 Issued
Array ( [id] => 11776228 [patent_doc_number] => 09385181 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-05 [patent_title] => 'Semiconductor diode and method of manufacturing a semiconductor diode' [patent_app_type] => utility [patent_app_number] => 14/162311 [patent_app_country] => US [patent_app_date] => 2014-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 5185 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14162311 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/162311
Semiconductor diode and method of manufacturing a semiconductor diode Jan 22, 2014 Issued
Array ( [id] => 11637831 [patent_doc_number] => 09659815 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-23 [patent_title] => 'System, method, and computer program product for a cavity package-on-package structure' [patent_app_type] => utility [patent_app_number] => 14/162696 [patent_app_country] => US [patent_app_date] => 2014-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5735 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14162696 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/162696
System, method, and computer program product for a cavity package-on-package structure Jan 22, 2014 Issued
Array ( [id] => 10138595 [patent_doc_number] => 09171917 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-27 [patent_title] => 'Edge termination configurations for high voltage semiconductor power devices' [patent_app_type] => utility [patent_app_number] => 14/162220 [patent_app_country] => US [patent_app_date] => 2014-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 2732 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14162220 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/162220
Edge termination configurations for high voltage semiconductor power devices Jan 22, 2014 Issued
Array ( [id] => 10518771 [patent_doc_number] => 09245825 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-26 [patent_title] => 'I/O pin capacitance reduction using TSVS' [patent_app_type] => utility [patent_app_number] => 14/161691 [patent_app_country] => US [patent_app_date] => 2014-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 7743 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14161691 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/161691
I/O pin capacitance reduction using TSVS Jan 22, 2014 Issued
Array ( [id] => 10321830 [patent_doc_number] => 20150206834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-23 [patent_title] => 'SEMICONDUCTOR DEVICE WITH COMBINED POWER AND GROUND RING STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/161706 [patent_app_country] => US [patent_app_date] => 2014-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4117 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14161706 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/161706
Semiconductor device with combined power and ground ring structure Jan 22, 2014 Issued
Array ( [id] => 11300819 [patent_doc_number] => 09508830 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-29 [patent_title] => 'Method of forming FinFET' [patent_app_type] => utility [patent_app_number] => 14/161730 [patent_app_country] => US [patent_app_date] => 2014-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2339 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14161730 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/161730
Method of forming FinFET Jan 22, 2014 Issued
Array ( [id] => 10073566 [patent_doc_number] => 09111931 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-18 [patent_title] => 'Method of forming an interconnect structure with high process margins' [patent_app_type] => utility [patent_app_number] => 14/161500 [patent_app_country] => US [patent_app_date] => 2014-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2670 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14161500 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/161500
Method of forming an interconnect structure with high process margins Jan 21, 2014 Issued
Array ( [id] => 10519077 [patent_doc_number] => 09246134 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-26 [patent_title] => 'Lamination transfer films for forming articles with engineered voids' [patent_app_type] => utility [patent_app_number] => 14/159300 [patent_app_country] => US [patent_app_date] => 2014-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 27 [patent_no_of_words] => 16066 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14159300 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/159300
Lamination transfer films for forming articles with engineered voids Jan 19, 2014 Issued
Array ( [id] => 10322002 [patent_doc_number] => 20150207006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-23 [patent_title] => 'SYSTEM AND METHOD FOR TRAPPING LIGHT IN A SOLAR CELL' [patent_app_type] => utility [patent_app_number] => 14/159002 [patent_app_country] => US [patent_app_date] => 2014-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5884 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14159002 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/159002
SYSTEM AND METHOD FOR TRAPPING LIGHT IN A SOLAR CELL Jan 19, 2014 Abandoned
Array ( [id] => 10597393 [patent_doc_number] => 09318488 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-19 [patent_title] => 'Semiconductor device and formation thereof' [patent_app_type] => utility [patent_app_number] => 14/147851 [patent_app_country] => US [patent_app_date] => 2014-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 5558 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14147851 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/147851
Semiconductor device and formation thereof Jan 5, 2014 Issued
Array ( [id] => 10309382 [patent_doc_number] => 20150194382 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-09 [patent_title] => 'INTERCONNECT AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/146911 [patent_app_country] => US [patent_app_date] => 2014-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3860 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14146911 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/146911
INTERCONNECT AND METHOD OF FABRICATING THE SAME Jan 2, 2014 Abandoned
Array ( [id] => 10053617 [patent_doc_number] => 09093503 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-07-28 [patent_title] => 'Semiconductor chip with a dual damascene wire and through-substrate via (TSV) structure' [patent_app_type] => utility [patent_app_number] => 14/146788 [patent_app_country] => US [patent_app_date] => 2014-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 26 [patent_no_of_words] => 11501 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14146788 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/146788
Semiconductor chip with a dual damascene wire and through-substrate via (TSV) structure Jan 2, 2014 Issued
Array ( [id] => 10302896 [patent_doc_number] => 20150187896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'SILICIDE PROTECTION DURING CONTACT METALLIZATION AND RESULTING SEMICONDUCTOR STRUCTURES' [patent_app_type] => utility [patent_app_number] => 14/146399 [patent_app_country] => US [patent_app_date] => 2014-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8669 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14146399 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/146399
Silicide protection during contact metallization and resulting semiconductor structures Jan 1, 2014 Issued
Array ( [id] => 10518941 [patent_doc_number] => 09245996 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-26 [patent_title] => 'Lateral double-diffused metal-oxide-semiconudctor transistor device and layout pattern for LDMOS transistor device' [patent_app_type] => utility [patent_app_number] => 14/146012 [patent_app_country] => US [patent_app_date] => 2014-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3701 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14146012 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/146012
Lateral double-diffused metal-oxide-semiconudctor transistor device and layout pattern for LDMOS transistor device Jan 1, 2014 Issued
Array ( [id] => 10195884 [patent_doc_number] => 09224799 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-29 [patent_title] => 'Capacitors including inner and outer electrodes' [patent_app_type] => utility [patent_app_number] => 14/145117 [patent_app_country] => US [patent_app_date] => 2013-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6712 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14145117 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/145117
Capacitors including inner and outer electrodes Dec 30, 2013 Issued
Array ( [id] => 10302874 [patent_doc_number] => 20150187874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'Field-Effect Semiconductor Device and Manufacturing Therefor' [patent_app_type] => utility [patent_app_number] => 14/145166 [patent_app_country] => US [patent_app_date] => 2013-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 13396 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14145166 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/145166
Field-effect semiconductor device and manufacturing therefor Dec 30, 2013 Issued
Array ( [id] => 10638608 [patent_doc_number] => 09356120 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-31 [patent_title] => 'Metal gate transistor and method for tuning metal gate profile' [patent_app_type] => utility [patent_app_number] => 14/145684 [patent_app_country] => US [patent_app_date] => 2013-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4335 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14145684 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/145684
Metal gate transistor and method for tuning metal gate profile Dec 30, 2013 Issued
Array ( [id] => 9710634 [patent_doc_number] => 08835202 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-16 [patent_title] => 'Structure and method for LED with phosphor coating' [patent_app_type] => utility [patent_app_number] => 14/140906 [patent_app_country] => US [patent_app_date] => 2013-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 8221 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14140906 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/140906
Structure and method for LED with phosphor coating Dec 25, 2013 Issued
Array ( [id] => 9627051 [patent_doc_number] => 08796734 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-05 [patent_title] => 'Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication' [patent_app_type] => utility [patent_app_number] => 14/104924 [patent_app_country] => US [patent_app_date] => 2013-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 43 [patent_no_of_words] => 15263 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14104924 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/104924
Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication Dec 11, 2013 Issued
Menu