Lalrinfamkim Hmar Malsawma

Array ( [id] => 9515400 [patent_doc_number] => 20140151892 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-05 [patent_title] => 'THREE DIMENSIONAL THROUGH-SILICON VIA CONSTRUCTION' [patent_app_type] => utility [patent_app_number] => 13/690364 [patent_app_country] => US [patent_app_date] => 2012-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2400 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13690364 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10845031 [patent_doc_number] => 08872211 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-28 [patent_title] => 'Element-connecting board, producing method thereof, and light-emitting diode device' [patent_app_type] => utility [patent_app_number] => 13/690494 [patent_app_country] => US [patent_app_date] => 2012-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12437 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13690494 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9515316 [patent_doc_number] => 20140151808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-05 [patent_title] => 'BULK FINFET ESD DEVICE' [patent_app_type] => utility [patent_app_number] => 13/690179 [patent_app_country] => US [patent_app_date] => 2012-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 1967 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13690179 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9515891 [patent_doc_number] => 20140152383 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-05 [patent_title] => 'INTEGRATED CIRCUITS AND SYSTEMS AND METHODS FOR PRODUCING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/690407 [patent_app_country] => US [patent_app_date] => 2012-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13264 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13690407 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9850754 [patent_doc_number] => 08952491 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-10 [patent_title] => 'Capacitive element' [patent_app_type] => utility [patent_app_number] => 13/690241 [patent_app_country] => US [patent_app_date] => 2012-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 5714 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13690241 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9582091 [patent_doc_number] => 08772094 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-08 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/681895 [patent_app_country] => US [patent_app_date] => 2012-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 45 [patent_no_of_words] => 33705 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13681895 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9648559 [patent_doc_number] => 08802570 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-12 [patent_title] => 'Pattern forming method' [patent_app_type] => utility [patent_app_number] => 13/682619 [patent_app_country] => US [patent_app_date] => 2012-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 8702 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13682619 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9850171 [patent_doc_number] => 08951899 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-10 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/681888 [patent_app_country] => US [patent_app_date] => 2012-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 37 [patent_no_of_words] => 22036 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13681888 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8981924 [patent_doc_number] => 08513038 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-20 [patent_title] => 'Method of manufacturing organic electroluminescent device' [patent_app_type] => utility [patent_app_number] => 13/681879 [patent_app_country] => US [patent_app_date] => 2012-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 24 [patent_no_of_words] => 9659 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13681879 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9491132 [patent_doc_number] => 20140141538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-22 [patent_title] => 'METHODS OF CHARACTERIZING SEMICONDUCTOR LIGHT-EMITTING DEVICES BASED ON PRODUCT WAFER CHARACTERISTICS' [patent_app_type] => utility [patent_app_number] => 13/681994 [patent_app_country] => US [patent_app_date] => 2012-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8231 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13681994 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9488431 [patent_doc_number] => 20140138837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-22 [patent_title] => 'SANDWICHED DIFFUSION BARRIER AND METAL LINER FOR AN INTERCONNECT STRUCTURE' [patent_app_type] => utility [patent_app_number] => 13/682326 [patent_app_country] => US [patent_app_date] => 2012-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3706 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13682326 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9608103 [patent_doc_number] => 08785269 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-22 [patent_title] => 'Method for manufacturing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/681844 [patent_app_country] => US [patent_app_date] => 2012-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 26 [patent_no_of_words] => 4263 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13681844 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8788891 [patent_doc_number] => 20130105860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-02 [patent_title] => 'Lattice-Mismatched Semiconductor Structures with Reduced Dislocation Defect Densities and Related Methods for Device Fabrication' [patent_app_type] => utility [patent_app_number] => 13/681214 [patent_app_country] => US [patent_app_date] => 2012-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 15273 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13681214 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9145376 [patent_doc_number] => 20130299899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-14 [patent_title] => 'Power Semiconductor Devices and Methods' [patent_app_type] => utility [patent_app_number] => 13/670019 [patent_app_country] => US [patent_app_date] => 2012-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 7726 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13670019 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10831970 [patent_doc_number] => 08860142 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-14 [patent_title] => 'Method and apparatus to reduce thermal variations within an integrated circuit die using thermal proximity correction' [patent_app_type] => utility [patent_app_number] => 13/648905 [patent_app_country] => US [patent_app_date] => 2012-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3934 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13648905 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8920832 [patent_doc_number] => 08486764 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-07-16 [patent_title] => 'Wafer level package and fabrication method' [patent_app_type] => utility [patent_app_number] => 13/627815 [patent_app_country] => US [patent_app_date] => 2012-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 7382 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13627815 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9389251 [patent_doc_number] => 08685849 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-01 [patent_title] => 'Semiconductor device with buffer layer' [patent_app_type] => utility [patent_app_number] => 13/626762 [patent_app_country] => US [patent_app_date] => 2012-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3111 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13626762 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8612343 [patent_doc_number] => 20130017655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-17 [patent_title] => 'DEVICES WITH NANOCRYSTALS AND METHODS OF FORMATION' [patent_app_type] => utility [patent_app_number] => 13/614794 [patent_app_country] => US [patent_app_date] => 2012-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4706 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13614794 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8738838 [patent_doc_number] => 08410612 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-02 [patent_title] => 'Interconnect regions' [patent_app_type] => utility [patent_app_number] => 13/607407 [patent_app_country] => US [patent_app_date] => 2012-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3401 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13607407 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9300243 [patent_doc_number] => 08648474 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-11 [patent_title] => 'Lead frame land grid array' [patent_app_type] => utility [patent_app_number] => 13/603311 [patent_app_country] => US [patent_app_date] => 2012-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 27 [patent_no_of_words] => 5634 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13603311 [rel_patent_id] =>[rel_patent_doc_number] =>)