Search

Lalrinfamkim Hmar Malsawma

Examiner (ID: 15570)

Most Active Art Unit
2892
Art Unit(s)
2825, 2823, 2892
Total Applications
1945
Issued Applications
1698
Pending Applications
102
Abandoned Applications
180

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8328557 [patent_doc_number] => 08236653 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-07 [patent_title] => 'Configuration and method to form MOSFET devices with low resistance silicide gate and mesa contact regions' [patent_app_type] => utility [patent_app_number] => 13/361950 [patent_app_country] => US [patent_app_date] => 2012-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 25 [patent_no_of_words] => 3185 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13361950 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/361950
Configuration and method to form MOSFET devices with low resistance silicide gate and mesa contact regions Jan 30, 2012 Issued
Array ( [id] => 8469689 [patent_doc_number] => 08298866 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-10-30 [patent_title] => 'Wafer level package and fabrication method' [patent_app_type] => utility [patent_app_number] => 13/358947 [patent_app_country] => US [patent_app_date] => 2012-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 7347 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13358947 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/358947
Wafer level package and fabrication method Jan 25, 2012 Issued
Array ( [id] => 8422276 [patent_doc_number] => 08278764 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-10-02 [patent_title] => 'Stub minimization for multi-die wirebond assemblies with orthogonal windows' [patent_app_type] => utility [patent_app_number] => 13/354772 [patent_app_country] => US [patent_app_date] => 2012-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 37 [patent_no_of_words] => 22176 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13354772 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/354772
Stub minimization for multi-die wirebond assemblies with orthogonal windows Jan 19, 2012 Issued
Array ( [id] => 8896621 [patent_doc_number] => 08476143 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-02 [patent_title] => 'Deep contacts of integrated electronic devices based on regions implanted through trenches' [patent_app_type] => utility [patent_app_number] => 13/349416 [patent_app_country] => US [patent_app_date] => 2012-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 6931 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13349416 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/349416
Deep contacts of integrated electronic devices based on regions implanted through trenches Jan 11, 2012 Issued
Array ( [id] => 8876365 [patent_doc_number] => 08471332 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-25 [patent_title] => 'Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout' [patent_app_type] => utility [patent_app_number] => 13/349288 [patent_app_country] => US [patent_app_date] => 2012-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 42 [patent_no_of_words] => 5650 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13349288 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/349288
Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout Jan 11, 2012 Issued
Array ( [id] => 8896621 [patent_doc_number] => 08476143 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-02 [patent_title] => 'Deep contacts of integrated electronic devices based on regions implanted through trenches' [patent_app_type] => utility [patent_app_number] => 13/349416 [patent_app_country] => US [patent_app_date] => 2012-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 6931 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13349416 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/349416
Deep contacts of integrated electronic devices based on regions implanted through trenches Jan 11, 2012 Issued
Array ( [id] => 8317866 [patent_doc_number] => 08232644 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-31 [patent_title] => 'Wafer level package having a stress relief spacer and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 13/346191 [patent_app_country] => US [patent_app_date] => 2012-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 6981 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13346191 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/346191
Wafer level package having a stress relief spacer and manufacturing method thereof Jan 8, 2012 Issued
Array ( [id] => 10538058 [patent_doc_number] => 09263696 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-16 [patent_title] => 'Organic semiconductor component comprising a doped hole conductor layer' [patent_app_type] => utility [patent_app_number] => 13/982053 [patent_app_country] => US [patent_app_date] => 2012-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 5359 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13982053 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/982053
Organic semiconductor component comprising a doped hole conductor layer Jan 4, 2012 Issued
Array ( [id] => 8317869 [patent_doc_number] => 08232651 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-31 [patent_title] => 'Bond pad for wafer and package for CMOS imager' [patent_app_type] => utility [patent_app_number] => 13/343422 [patent_app_country] => US [patent_app_date] => 2012-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 3579 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13343422 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/343422
Bond pad for wafer and package for CMOS imager Jan 3, 2012 Issued
Array ( [id] => 10501067 [patent_doc_number] => 09229466 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-05 [patent_title] => 'Fully integrated voltage regulators for multi-stack integrated circuit architectures' [patent_app_type] => utility [patent_app_number] => 13/977460 [patent_app_country] => US [patent_app_date] => 2011-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3287 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13977460 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/977460
Fully integrated voltage regulators for multi-stack integrated circuit architectures Dec 30, 2011 Issued
Array ( [id] => 9145290 [patent_doc_number] => 20130299813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-14 [patent_title] => 'ORGANIC EL PANEL AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/982007 [patent_app_country] => US [patent_app_date] => 2011-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 10263 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13982007 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/982007
Organic EL panel and manufacturing method thereof Dec 1, 2011 Issued
Array ( [id] => 8237306 [patent_doc_number] => 20120146035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-14 [patent_title] => 'DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/308607 [patent_app_country] => US [patent_app_date] => 2011-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 17672 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13308607 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/308607
Display device and method for manufacturing the same Nov 30, 2011 Issued
Array ( [id] => 8730148 [patent_doc_number] => 20130075717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-28 [patent_title] => 'THIN FILM TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 13/308549 [patent_app_country] => US [patent_app_date] => 2011-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1735 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13308549 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/308549
THIN FILM TRANSISTOR Nov 30, 2011 Abandoned
Array ( [id] => 8850964 [patent_doc_number] => 20130140639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-06 [patent_title] => 'HIGH GATE DENSITY DEVICES AND METHODS' [patent_app_type] => utility [patent_app_number] => 13/308671 [patent_app_country] => US [patent_app_date] => 2011-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3884 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13308671 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/308671
High gate density devices and methods Nov 30, 2011 Issued
Array ( [id] => 10831884 [patent_doc_number] => 08860056 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-14 [patent_title] => 'Structure and method for LED with phosphor coating' [patent_app_type] => utility [patent_app_number] => 13/308715 [patent_app_country] => US [patent_app_date] => 2011-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 8177 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13308715 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/308715
Structure and method for LED with phosphor coating Nov 30, 2011 Issued
Array ( [id] => 8217318 [patent_doc_number] => 20120132971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-31 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/307775 [patent_app_country] => US [patent_app_date] => 2011-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 75 [patent_figures_cnt] => 75 [patent_no_of_words] => 30489 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13307775 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/307775
Semiconductor device and method of forming the same Nov 29, 2011 Issued
Array ( [id] => 8838863 [patent_doc_number] => 20130134491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-30 [patent_title] => 'POLYSILICON/METAL CONTACT RESISTANCE IN DEEP TRENCH' [patent_app_type] => utility [patent_app_number] => 13/307874 [patent_app_country] => US [patent_app_date] => 2011-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10731 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13307874 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/307874
Polysilicon/metal contact resistance in deep trench Nov 29, 2011 Issued
Array ( [id] => 9239724 [patent_doc_number] => 08604518 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-10 [patent_title] => 'Split-channel transistor and methods for forming the same' [patent_app_type] => utility [patent_app_number] => 13/307738 [patent_app_country] => US [patent_app_date] => 2011-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 3093 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13307738 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/307738
Split-channel transistor and methods for forming the same Nov 29, 2011 Issued
Array ( [id] => 9112956 [patent_doc_number] => 08569125 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-29 [patent_title] => 'FinFET with improved gate planarity' [patent_app_type] => utility [patent_app_number] => 13/307931 [patent_app_country] => US [patent_app_date] => 2011-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 3882 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13307931 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/307931
FinFET with improved gate planarity Nov 29, 2011 Issued
Array ( [id] => 8838832 [patent_doc_number] => 20130134460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-30 [patent_title] => 'COATED COLOR-CONVERTING PARTICLES AND ASSOCIATED DEVICES, SYSTEMS, AND METHODS' [patent_app_type] => utility [patent_app_number] => 13/308199 [patent_app_country] => US [patent_app_date] => 2011-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5963 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13308199 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/308199
Coated color-converting particles and associated devices, systems, and methods Nov 29, 2011 Issued
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