Search

Lalrinfamkim Hmar Malsawma

Examiner (ID: 2370)

Most Active Art Unit
2892
Art Unit(s)
2823, 2892, 2825
Total Applications
1951
Issued Applications
1709
Pending Applications
105
Abandoned Applications
179

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8483372 [patent_doc_number] => 20120282779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-08 [patent_title] => 'SIDEWALL IMAGE TRANSFER PROCESS EMPLOYING A CAP MATERIAL LAYER FOR A METAL NITRIDE LAYER' [patent_app_type] => utility [patent_app_number] => 13/102224 [patent_app_country] => US [patent_app_date] => 2011-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6209 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13102224 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/102224
Sidewall image transfer process employing a cap material layer for a metal nitride layer May 5, 2011 Issued
Array ( [id] => 8543227 [patent_doc_number] => 08318516 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-27 [patent_title] => 'Method of wafer level purifying light color emitting from a light emitting semiconductor wafer' [patent_app_type] => utility [patent_app_number] => 13/102356 [patent_app_country] => US [patent_app_date] => 2011-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 6 [patent_no_of_words] => 2594 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13102356 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/102356
Method of wafer level purifying light color emitting from a light emitting semiconductor wafer May 5, 2011 Issued
Array ( [id] => 9389209 [patent_doc_number] => 08685807 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-01 [patent_title] => 'Method of forming metal gates and metal contacts in a common fill process' [patent_app_type] => utility [patent_app_number] => 13/100798 [patent_app_country] => US [patent_app_date] => 2011-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3015 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13100798 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/100798
Method of forming metal gates and metal contacts in a common fill process May 3, 2011 Issued
Array ( [id] => 8356616 [patent_doc_number] => 20120211770 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-23 [patent_title] => 'SEMICONDUCTOR DEVICE, COMBINED SUBSTRATE, AND METHODS FOR MANUFACTURING THEM' [patent_app_type] => utility [patent_app_number] => 13/504410 [patent_app_country] => US [patent_app_date] => 2011-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 17301 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13504410 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/504410
SEMICONDUCTOR DEVICE, COMBINED SUBSTRATE, AND METHODS FOR MANUFACTURING THEM May 1, 2011 Abandoned
Array ( [id] => 7561340 [patent_doc_number] => 20110275173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-10 [patent_title] => 'ISOLATION BY IMPLANTATION IN LED ARRAY MANUFACTURING' [patent_app_type] => utility [patent_app_number] => 13/098942 [patent_app_country] => US [patent_app_date] => 2011-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3712 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0275/20110275173.pdf [firstpage_image] =>[orig_patent_app_number] => 13098942 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/098942
Isolation by implantation in LED array manufacturing May 1, 2011 Issued
Array ( [id] => 8708070 [patent_doc_number] => 20130065359 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-14 [patent_title] => 'SELECTIVELY ETCHING OF A CARBON NANO TUBES (CNT) POLYMER MATRIX ON A PLASTIC SUBSTRUCTURE' [patent_app_type] => utility [patent_app_number] => 13/699092 [patent_app_country] => US [patent_app_date] => 2011-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 7349 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13699092 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/699092
Selectively etching of a carbon nano tubes (CNT) polymer matrix on a plastic substructure Apr 25, 2011 Issued
Array ( [id] => 8446764 [patent_doc_number] => 08288818 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-16 [patent_title] => 'Devices with nanocrystals and methods of formation' [patent_app_type] => utility [patent_app_number] => 13/088777 [patent_app_country] => US [patent_app_date] => 2011-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4688 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13088777 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/088777
Devices with nanocrystals and methods of formation Apr 17, 2011 Issued
Array ( [id] => 10028780 [patent_doc_number] => 09070689 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-30 [patent_title] => 'Structure for interconnecting copper with low dielectric constant medium and the integration method thereof' [patent_app_type] => utility [patent_app_number] => 13/381182 [patent_app_country] => US [patent_app_date] => 2011-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1217 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13381182 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/381182
Structure for interconnecting copper with low dielectric constant medium and the integration method thereof Apr 7, 2011 Issued
Array ( [id] => 8933204 [patent_doc_number] => 08492906 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-23 [patent_title] => 'Lead frame ball grid array with traces under die' [patent_app_type] => utility [patent_app_number] => 13/080512 [patent_app_country] => US [patent_app_date] => 2011-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 56 [patent_no_of_words] => 11595 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13080512 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/080512
Lead frame ball grid array with traces under die Apr 4, 2011 Issued
Array ( [id] => 6176317 [patent_doc_number] => 20110177659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-21 [patent_title] => 'SOI BODY CONTACT USING E-DRAM TECHNOLOGY' [patent_app_type] => utility [patent_app_number] => 13/075552 [patent_app_country] => US [patent_app_date] => 2011-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2838 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20110177659.pdf [firstpage_image] =>[orig_patent_app_number] => 13075552 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/075552
SOI body contact using E-DRAM technology Mar 29, 2011 Issued
Array ( [id] => 7773844 [patent_doc_number] => 08119455 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-02-21 [patent_title] => 'Wafer level package fabrication method' [patent_app_type] => utility [patent_app_number] => 13/065296 [patent_app_country] => US [patent_app_date] => 2011-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 7303 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/119/08119455.pdf [firstpage_image] =>[orig_patent_app_number] => 13065296 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/065296
Wafer level package fabrication method Mar 17, 2011 Issued
Array ( [id] => 10876747 [patent_doc_number] => 08901535 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-02 [patent_title] => 'Semiconductor nanoparticle assembly' [patent_app_type] => utility [patent_app_number] => 13/818849 [patent_app_country] => US [patent_app_date] => 2011-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4951 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13818849 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/818849
Semiconductor nanoparticle assembly Mar 14, 2011 Issued
Array ( [id] => 5963511 [patent_doc_number] => 20110147931 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-23 [patent_title] => 'LEAD FRAME LAND GRID ARRAY WITH ROUTING CONNECTOR TRACE UNDER UNIT' [patent_app_type] => utility [patent_app_number] => 13/040112 [patent_app_country] => US [patent_app_date] => 2011-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 7876 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0147/20110147931.pdf [firstpage_image] =>[orig_patent_app_number] => 13040112 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/040112
Lead frame land grid array with routing connector trace under unit Mar 2, 2011 Issued
Array ( [id] => 7740300 [patent_doc_number] => 08105895 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-31 [patent_title] => 'Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout' [patent_app_type] => utility [patent_app_number] => 12/932163 [patent_app_country] => US [patent_app_date] => 2011-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 42 [patent_no_of_words] => 5569 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/105/08105895.pdf [firstpage_image] =>[orig_patent_app_number] => 12932163 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/932163
Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout Feb 16, 2011 Issued
Array ( [id] => 6213036 [patent_doc_number] => 20110136336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-09 [patent_title] => 'METHODS OF FORMING CONDUCTIVE VIAS' [patent_app_type] => utility [patent_app_number] => 13/029950 [patent_app_country] => US [patent_app_date] => 2011-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10330 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20110136336.pdf [firstpage_image] =>[orig_patent_app_number] => 13029950 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/029950
Methods of forming conductive vias Feb 16, 2011 Issued
Array ( [id] => 8689836 [patent_doc_number] => 08389363 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-05 [patent_title] => 'Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates' [patent_app_type] => utility [patent_app_number] => 13/017508 [patent_app_country] => US [patent_app_date] => 2011-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 5104 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13017508 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/017508
Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates Jan 30, 2011 Issued
Array ( [id] => 8982682 [patent_doc_number] => 08513802 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-20 [patent_title] => 'Multi-chip package having semiconductor chips of different thicknesses from each other and related device' [patent_app_type] => utility [patent_app_number] => 13/013290 [patent_app_country] => US [patent_app_date] => 2011-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 7015 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13013290 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/013290
Multi-chip package having semiconductor chips of different thicknesses from each other and related device Jan 24, 2011 Issued
Array ( [id] => 6055229 [patent_doc_number] => 20110111589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-12 [patent_title] => 'BARRIER-METAL-FREE COPPER CAMASCENCE TECHNOLOGY USING ATOMIC HYDROGEN ENHANCED REFLOW' [patent_app_type] => utility [patent_app_number] => 13/005231 [patent_app_country] => US [patent_app_date] => 2011-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4324 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20110111589.pdf [firstpage_image] =>[orig_patent_app_number] => 13005231 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/005231
Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow Jan 11, 2011 Issued
Array ( [id] => 8458602 [patent_doc_number] => 08294273 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-23 [patent_title] => 'Methods for fabricating and filling conductive vias and conductive vias so formed' [patent_app_type] => utility [patent_app_number] => 12/985570 [patent_app_country] => US [patent_app_date] => 2011-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 59 [patent_no_of_words] => 10379 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12985570 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/985570
Methods for fabricating and filling conductive vias and conductive vias so formed Jan 5, 2011 Issued
Array ( [id] => 6114643 [patent_doc_number] => 20110074029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-31 [patent_title] => 'FLIP-CHIP PACKAGE COVERED WITH TAPE' [patent_app_type] => utility [patent_app_number] => 12/962479 [patent_app_country] => US [patent_app_date] => 2010-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2984 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20110074029.pdf [firstpage_image] =>[orig_patent_app_number] => 12962479 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/962479
Flip-chip package covered with tape Dec 6, 2010 Issued
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