
Lalrinfamkim Hmar Malsawma
Examiner (ID: 5479)
| Most Active Art Unit | 2892 |
| Art Unit(s) | 2825, 2892, 2823 |
| Total Applications | 2001 |
| Issued Applications | 1735 |
| Pending Applications | 112 |
| Abandoned Applications | 179 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8982682
[patent_doc_number] => 08513802
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-08-20
[patent_title] => 'Multi-chip package having semiconductor chips of different thicknesses from each other and related device'
[patent_app_type] => utility
[patent_app_number] => 13/013290
[patent_app_country] => US
[patent_app_date] => 2011-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 14
[patent_no_of_words] => 7015
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[patent_words_short_claim] => 137
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13013290
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/013290 | Multi-chip package having semiconductor chips of different thicknesses from each other and related device | Jan 24, 2011 | Issued |
Array
(
[id] => 6055229
[patent_doc_number] => 20110111589
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-05-12
[patent_title] => 'BARRIER-METAL-FREE COPPER CAMASCENCE TECHNOLOGY USING ATOMIC HYDROGEN ENHANCED REFLOW'
[patent_app_type] => utility
[patent_app_number] => 13/005231
[patent_app_country] => US
[patent_app_date] => 2011-01-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] => publications/A1/0111/20110111589.pdf
[firstpage_image] =>[orig_patent_app_number] => 13005231
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/005231 | Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow | Jan 11, 2011 | Issued |
Array
(
[id] => 8458602
[patent_doc_number] => 08294273
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-10-23
[patent_title] => 'Methods for fabricating and filling conductive vias and conductive vias so formed'
[patent_app_type] => utility
[patent_app_number] => 12/985570
[patent_app_country] => US
[patent_app_date] => 2011-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/985570 | Methods for fabricating and filling conductive vias and conductive vias so formed | Jan 5, 2011 | Issued |
Array
(
[id] => 6114643
[patent_doc_number] => 20110074029
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-03-31
[patent_title] => 'FLIP-CHIP PACKAGE COVERED WITH TAPE'
[patent_app_type] => utility
[patent_app_number] => 12/962479
[patent_app_country] => US
[patent_app_date] => 2010-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[pdf_file] => publications/A1/0074/20110074029.pdf
[firstpage_image] =>[orig_patent_app_number] => 12962479
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/962479 | Flip-chip package covered with tape | Dec 6, 2010 | Issued |
Array
(
[id] => 6026892
[patent_doc_number] => 20110079825
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-04-07
[patent_title] => 'Cascoded high voltage junction field effect transistor'
[patent_app_type] => utility
[patent_app_number] => 12/928107
[patent_app_country] => US
[patent_app_date] => 2010-12-02
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/928107 | Cascoded high voltage junction field effect transistor | Dec 1, 2010 | Issued |
Array
(
[id] => 8863158
[patent_doc_number] => 20130146861
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[patent_kind] => A1
[patent_issue_date] => 2013-06-13
[patent_title] => 'ORGANIC EL PANEL, DISPLAY DEVICE USING SAME, AND METHOD FOR PRODUCING ORGANIC EL PANEL'
[patent_app_type] => utility
[patent_app_number] => 13/818797
[patent_app_country] => US
[patent_app_date] => 2010-11-24
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/818797 | Organic el panel, display device using same, and method for producing organic el panel | Nov 23, 2010 | Issued |
Array
(
[id] => 4605036
[patent_doc_number] => 07986017
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[patent_issue_date] => 2011-07-26
[patent_title] => 'Semiconductor sensor and method for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 12/951436
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/951436 | Semiconductor sensor and method for manufacturing the same | Nov 21, 2010 | Issued |
Array
(
[id] => 7740320
[patent_doc_number] => 08105905
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[patent_issue_date] => 2012-01-31
[patent_title] => 'Configuration and method to form MOSFET devices with low resistance silicide gate and mesa contact regions'
[patent_app_type] => utility
[patent_app_number] => 12/927177
[patent_app_country] => US
[patent_app_date] => 2010-11-08
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/927177 | Configuration and method to form MOSFET devices with low resistance silicide gate and mesa contact regions | Nov 7, 2010 | Issued |
Array
(
[id] => 5929426
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[patent_issue_date] => 2011-02-17
[patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME'
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[patent_app_number] => 12/912609
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/912609 | Semiconductor device and manufacturing method of the same | Oct 25, 2010 | Issued |
Array
(
[id] => 5948544
[patent_doc_number] => 20110031621
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[patent_kind] => A1
[patent_issue_date] => 2011-02-10
[patent_title] => 'WAFER LEVEL PACKAGE HAVING A STRESS RELIEF SPACER AND MANUFACTURING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 12/910260
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/910260 | Wafer level package having a stress relief spacer and manufacturing method thereof | Oct 21, 2010 | Issued |
Array
(
[id] => 5972739
[patent_doc_number] => 20110068482
[patent_country] => US
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[patent_issue_date] => 2011-03-24
[patent_title] => 'SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE'
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Array
(
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Array
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Array
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Array
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Array
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Array
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Array
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