
Lalrinfamkim Hmar Malsawma
Examiner (ID: 2370)
| Most Active Art Unit | 2892 |
| Art Unit(s) | 2823, 2892, 2825 |
| Total Applications | 1951 |
| Issued Applications | 1709 |
| Pending Applications | 105 |
| Abandoned Applications | 179 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6562588
[patent_doc_number] => 20100059829
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-03-11
[patent_title] => 'PROCESS FOR MANUFACTURING A MEMORY DEVICE INCLUDING A VERTICAL BIPOLAR JUNCTION TRANSISTOR AND A CMOS TRANSISTOR WITH SPACERS'
[patent_app_type] => utility
[patent_app_number] => 12/557396
[patent_app_country] => US
[patent_app_date] => 2009-09-10
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0059/20100059829.pdf
[firstpage_image] =>[orig_patent_app_number] => 12557396
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/557396 | Process for manufacturing a memory device including a vertical bipolar junction transistor and a CMOS transistor with spacers | Sep 9, 2009 | Issued |
Array
(
[id] => 6004154
[patent_doc_number] => 20110057307
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[patent_kind] => A1
[patent_issue_date] => 2011-03-10
[patent_title] => 'Semiconductor Chip with Stair Arrangement Bump Structures'
[patent_app_type] => utility
[patent_app_number] => 12/557336
[patent_app_country] => US
[patent_app_date] => 2009-09-10
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/557336 | Semiconductor Chip with Stair Arrangement Bump Structures | Sep 9, 2009 | Abandoned |
Array
(
[id] => 6007556
[patent_doc_number] => 20110059587
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[patent_kind] => A1
[patent_issue_date] => 2011-03-10
[patent_title] => 'DEVICE HAVING SELF-ALIGNED DOUBLE GATE FORMED BY BACKSIDE ENGINEERING, AND DEVICE HAVING SUPER-STEEP RETROGRADED ISLAND'
[patent_app_type] => utility
[patent_app_number] => 12/556604
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[firstpage_image] =>[orig_patent_app_number] => 12556604
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/556604 | Device having self-aligned double gate formed by backside engineering, and device having super-steep retrograded island | Sep 9, 2009 | Issued |
Array
(
[id] => 8317344
[patent_doc_number] => 08232121
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-07-31
[patent_title] => 'Zinc oxide-based semiconductor device and method for producing same'
[patent_app_type] => utility
[patent_app_number] => 12/556914
[patent_app_country] => US
[patent_app_date] => 2009-09-10
[patent_effective_date] => 0000-00-00
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Array
(
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[patent_doc_number] => 20110008921
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[patent_kind] => A1
[patent_issue_date] => 2011-01-13
[patent_title] => 'Method for Fabricating Flexible Display Device'
[patent_app_type] => utility
[patent_app_number] => 12/556692
[patent_app_country] => US
[patent_app_date] => 2009-09-10
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Array
(
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[patent_doc_number] => 20100216270
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[patent_issue_date] => 2010-08-26
[patent_title] => 'METHOD FOR MANUFACTURING LIGHT EMITTING DIODE'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/557023 | Method for manufacturing light emitting diode | Sep 9, 2009 | Issued |
Array
(
[id] => 7751527
[patent_doc_number] => 08110498
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-02-07
[patent_title] => 'Method for passivating exposed copper surfaces in a metallization layer of a semiconductor device'
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[patent_app_number] => 12/555844
[patent_app_country] => US
[patent_app_date] => 2009-09-09
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/555844 | Method for passivating exposed copper surfaces in a metallization layer of a semiconductor device | Sep 8, 2009 | Issued |
Array
(
[id] => 4608948
[patent_doc_number] => 07994045
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2011-08-09
[patent_title] => 'Bumped chip package fabrication method and structure'
[patent_app_type] => utility
[patent_app_number] => 12/555449
[patent_app_country] => US
[patent_app_date] => 2009-09-08
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/994/07994045.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/555449 | Bumped chip package fabrication method and structure | Sep 7, 2009 | Issued |
Array
(
[id] => 6294993
[patent_doc_number] => 20100065897
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[patent_kind] => A1
[patent_issue_date] => 2010-03-18
[patent_title] => 'CMOS Image Sensor and Method for Fabricating the Same'
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[patent_app_number] => 12/554683
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[patent_app_date] => 2009-09-04
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Array
(
[id] => 8328487
[patent_doc_number] => 08236583
[patent_country] => US
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[patent_issue_date] => 2012-08-07
[patent_title] => 'Method of separating light-emitting diode from a growth substrate'
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[patent_app_number] => 12/554578
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Array
(
[id] => 6512429
[patent_doc_number] => 20100261330
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[patent_kind] => A1
[patent_issue_date] => 2010-10-14
[patent_title] => 'METHOD OF MANUFACTURING NONVOLATILE STORAGE DEVICE'
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[patent_app_number] => 12/554319
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/554319 | Method of manufacturing nonvolatile storage device | Sep 3, 2009 | Issued |
Array
(
[id] => 6324391
[patent_doc_number] => 20100197132
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[patent_title] => 'Barrier-Metal-Free Copper Damascene Technology Using Atomic Hydrogen Enhanced Reflow'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/553691 | Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow | Sep 2, 2009 | Issued |
Array
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Array
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Array
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[patent_title] => 'INTEGRATED CIRCUIT CHIP WITH FETS HAVING MIXED BODY THICKNESSES AND METHOD OF MANUFACTURE THEREOF'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/541641 | Integrated circuit chip with FETs having mixed body thicknesses and method of manufacture thereof | Aug 13, 2009 | Issued |
Array
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Array
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Array
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Array
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[patent_issue_date] => 2010-01-14
[patent_title] => 'SEMICONDUCTOR CHIP, WIRING SUBSTRATE OF A SEMICONDUCTOR PACKAGE, SEMICONDUCTOR PACKAGE HAVING THE SEMICONDUCTOR CHIP AND DISPLAY DEVICE HAVING THE SEMICONDUCTOR PACKAGE'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/502324 | Semiconductor chip, wiring substrate of a semiconductor package, semiconductor package having the semiconductor chip and display device having the semiconductor package | Jul 13, 2009 | Issued |