Search

Lalrinfamkim Hmar Malsawma

Examiner (ID: 2370)

Most Active Art Unit
2892
Art Unit(s)
2823, 2892, 2825
Total Applications
1951
Issued Applications
1709
Pending Applications
105
Abandoned Applications
179

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6562588 [patent_doc_number] => 20100059829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-11 [patent_title] => 'PROCESS FOR MANUFACTURING A MEMORY DEVICE INCLUDING A VERTICAL BIPOLAR JUNCTION TRANSISTOR AND A CMOS TRANSISTOR WITH SPACERS' [patent_app_type] => utility [patent_app_number] => 12/557396 [patent_app_country] => US [patent_app_date] => 2009-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4295 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20100059829.pdf [firstpage_image] =>[orig_patent_app_number] => 12557396 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/557396
Process for manufacturing a memory device including a vertical bipolar junction transistor and a CMOS transistor with spacers Sep 9, 2009 Issued
Array ( [id] => 6004154 [patent_doc_number] => 20110057307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-10 [patent_title] => 'Semiconductor Chip with Stair Arrangement Bump Structures' [patent_app_type] => utility [patent_app_number] => 12/557336 [patent_app_country] => US [patent_app_date] => 2009-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4520 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20110057307.pdf [firstpage_image] =>[orig_patent_app_number] => 12557336 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/557336
Semiconductor Chip with Stair Arrangement Bump Structures Sep 9, 2009 Abandoned
Array ( [id] => 6007556 [patent_doc_number] => 20110059587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-10 [patent_title] => 'DEVICE HAVING SELF-ALIGNED DOUBLE GATE FORMED BY BACKSIDE ENGINEERING, AND DEVICE HAVING SUPER-STEEP RETROGRADED ISLAND' [patent_app_type] => utility [patent_app_number] => 12/556604 [patent_app_country] => US [patent_app_date] => 2009-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6962 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20110059587.pdf [firstpage_image] =>[orig_patent_app_number] => 12556604 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/556604
Device having self-aligned double gate formed by backside engineering, and device having super-steep retrograded island Sep 9, 2009 Issued
Array ( [id] => 8317344 [patent_doc_number] => 08232121 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-31 [patent_title] => 'Zinc oxide-based semiconductor device and method for producing same' [patent_app_type] => utility [patent_app_number] => 12/556914 [patent_app_country] => US [patent_app_date] => 2009-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 5885 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12556914 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/556914
Zinc oxide-based semiconductor device and method for producing same Sep 9, 2009 Issued
Array ( [id] => 6135313 [patent_doc_number] => 20110008921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-13 [patent_title] => 'Method for Fabricating Flexible Display Device' [patent_app_type] => utility [patent_app_number] => 12/556692 [patent_app_country] => US [patent_app_date] => 2009-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2096 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20110008921.pdf [firstpage_image] =>[orig_patent_app_number] => 12556692 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/556692
Method for fabricating flexible display device Sep 9, 2009 Issued
Array ( [id] => 6508253 [patent_doc_number] => 20100216270 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-26 [patent_title] => 'METHOD FOR MANUFACTURING LIGHT EMITTING DIODE' [patent_app_type] => utility [patent_app_number] => 12/557023 [patent_app_country] => US [patent_app_date] => 2009-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 2725 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20100216270.pdf [firstpage_image] =>[orig_patent_app_number] => 12557023 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/557023
Method for manufacturing light emitting diode Sep 9, 2009 Issued
Array ( [id] => 7751527 [patent_doc_number] => 08110498 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-07 [patent_title] => 'Method for passivating exposed copper surfaces in a metallization layer of a semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/555844 [patent_app_country] => US [patent_app_date] => 2009-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 6691 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/110/08110498.pdf [firstpage_image] =>[orig_patent_app_number] => 12555844 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/555844
Method for passivating exposed copper surfaces in a metallization layer of a semiconductor device Sep 8, 2009 Issued
Array ( [id] => 4608948 [patent_doc_number] => 07994045 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-08-09 [patent_title] => 'Bumped chip package fabrication method and structure' [patent_app_type] => utility [patent_app_number] => 12/555449 [patent_app_country] => US [patent_app_date] => 2009-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 26 [patent_no_of_words] => 7711 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/994/07994045.pdf [firstpage_image] =>[orig_patent_app_number] => 12555449 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/555449
Bumped chip package fabrication method and structure Sep 7, 2009 Issued
Array ( [id] => 6294993 [patent_doc_number] => 20100065897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-18 [patent_title] => 'CMOS Image Sensor and Method for Fabricating the Same' [patent_app_type] => utility [patent_app_number] => 12/554683 [patent_app_country] => US [patent_app_date] => 2009-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3085 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20100065897.pdf [firstpage_image] =>[orig_patent_app_number] => 12554683 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/554683
CMOS image sensor and method for fabricating the same Sep 3, 2009 Issued
Array ( [id] => 8328487 [patent_doc_number] => 08236583 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-07 [patent_title] => 'Method of separating light-emitting diode from a growth substrate' [patent_app_type] => utility [patent_app_number] => 12/554578 [patent_app_country] => US [patent_app_date] => 2009-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3922 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12554578 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/554578
Method of separating light-emitting diode from a growth substrate Sep 3, 2009 Issued
Array ( [id] => 6512429 [patent_doc_number] => 20100261330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-14 [patent_title] => 'METHOD OF MANUFACTURING NONVOLATILE STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 12/554319 [patent_app_country] => US [patent_app_date] => 2009-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6180 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0261/20100261330.pdf [firstpage_image] =>[orig_patent_app_number] => 12554319 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/554319
Method of manufacturing nonvolatile storage device Sep 3, 2009 Issued
Array ( [id] => 6324391 [patent_doc_number] => 20100197132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-05 [patent_title] => 'Barrier-Metal-Free Copper Damascene Technology Using Atomic Hydrogen Enhanced Reflow' [patent_app_type] => utility [patent_app_number] => 12/553691 [patent_app_country] => US [patent_app_date] => 2009-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4309 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20100197132.pdf [firstpage_image] =>[orig_patent_app_number] => 12553691 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/553691
Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow Sep 2, 2009 Issued
Array ( [id] => 8629810 [patent_doc_number] => 08361882 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-29 [patent_title] => 'Semiconductor device and method for manufacturing same' [patent_app_type] => utility [patent_app_number] => 13/139988 [patent_app_country] => US [patent_app_date] => 2009-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 38 [patent_no_of_words] => 8598 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13139988 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/139988
Semiconductor device and method for manufacturing same Aug 20, 2009 Issued
Array ( [id] => 7479789 [patent_doc_number] => 20110248252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-13 [patent_title] => 'ORGANIC EL ELEMENT AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/139857 [patent_app_country] => US [patent_app_date] => 2009-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7451 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20110248252.pdf [firstpage_image] =>[orig_patent_app_number] => 13139857 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/139857
ORGANIC EL ELEMENT AND METHOD FOR FABRICATING THE SAME Aug 16, 2009 Abandoned
Array ( [id] => 5364828 [patent_doc_number] => 20090302387 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-10 [patent_title] => 'INTEGRATED CIRCUIT CHIP WITH FETS HAVING MIXED BODY THICKNESSES AND METHOD OF MANUFACTURE THEREOF' [patent_app_type] => utility [patent_app_number] => 12/541641 [patent_app_country] => US [patent_app_date] => 2009-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3531 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0302/20090302387.pdf [firstpage_image] =>[orig_patent_app_number] => 12541641 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/541641
Integrated circuit chip with FETs having mixed body thicknesses and method of manufacture thereof Aug 13, 2009 Issued
Array ( [id] => 4533274 [patent_doc_number] => 07888164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-15 [patent_title] => 'Programmable via structure and method of fabricating same' [patent_app_type] => utility [patent_app_number] => 12/538120 [patent_app_country] => US [patent_app_date] => 2009-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 4219 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/888/07888164.pdf [firstpage_image] =>[orig_patent_app_number] => 12538120 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/538120
Programmable via structure and method of fabricating same Aug 7, 2009 Issued
Array ( [id] => 4573944 [patent_doc_number] => 07855111 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-21 [patent_title] => 'Border region defect reduction in hybrid orientation technology (HOT) direct silicon bonded (DSB) substrates' [patent_app_type] => utility [patent_app_number] => 12/538048 [patent_app_country] => US [patent_app_date] => 2009-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4148 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/855/07855111.pdf [firstpage_image] =>[orig_patent_app_number] => 12538048 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/538048
Border region defect reduction in hybrid orientation technology (HOT) direct silicon bonded (DSB) substrates Aug 6, 2009 Issued
Array ( [id] => 7752574 [patent_doc_number] => 08110870 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-07 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/502251 [patent_app_country] => US [patent_app_date] => 2009-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6193 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/110/08110870.pdf [firstpage_image] =>[orig_patent_app_number] => 12502251 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/502251
Semiconductor device Jul 13, 2009 Issued
Array ( [id] => 8029293 [patent_doc_number] => 08143731 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-27 [patent_title] => 'Integrated alignment and overlay mark' [patent_app_type] => utility [patent_app_number] => 12/502236 [patent_app_country] => US [patent_app_date] => 2009-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2175 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/143/08143731.pdf [firstpage_image] =>[orig_patent_app_number] => 12502236 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/502236
Integrated alignment and overlay mark Jul 13, 2009 Issued
Array ( [id] => 6463073 [patent_doc_number] => 20100006869 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-14 [patent_title] => 'SEMICONDUCTOR CHIP, WIRING SUBSTRATE OF A SEMICONDUCTOR PACKAGE, SEMICONDUCTOR PACKAGE HAVING THE SEMICONDUCTOR CHIP AND DISPLAY DEVICE HAVING THE SEMICONDUCTOR PACKAGE' [patent_app_type] => utility [patent_app_number] => 12/502324 [patent_app_country] => US [patent_app_date] => 2009-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8676 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20100006869.pdf [firstpage_image] =>[orig_patent_app_number] => 12502324 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/502324
Semiconductor chip, wiring substrate of a semiconductor package, semiconductor package having the semiconductor chip and display device having the semiconductor package Jul 13, 2009 Issued
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