Search

Lalrinfamkim Hmar Malsawma

Examiner (ID: 2370)

Most Active Art Unit
2892
Art Unit(s)
2823, 2892, 2825
Total Applications
1951
Issued Applications
1709
Pending Applications
105
Abandoned Applications
179

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 807323 [patent_doc_number] => 07420272 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-09-02 [patent_title] => 'Two-sided wafer escape package' [patent_app_type] => utility [patent_app_number] => 11/784979 [patent_app_country] => US [patent_app_date] => 2007-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 35 [patent_no_of_words] => 17116 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/420/07420272.pdf [firstpage_image] =>[orig_patent_app_number] => 11784979 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/784979
Two-sided wafer escape package Apr 8, 2007 Issued
Array ( [id] => 8533903 [patent_doc_number] => 08310060 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-11-13 [patent_title] => 'Lead frame land grid array' [patent_app_type] => utility [patent_app_number] => 11/731522 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 27 [patent_no_of_words] => 5599 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11731522 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/731522
Lead frame land grid array Mar 29, 2007 Issued
Array ( [id] => 8202897 [patent_doc_number] => 08188557 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-29 [patent_title] => 'Single die MEMS acoustic transducer and manufacturing method' [patent_app_type] => utility [patent_app_number] => 12/295220 [patent_app_country] => US [patent_app_date] => 2007-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 54 [patent_no_of_words] => 9148 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/188/08188557.pdf [firstpage_image] =>[orig_patent_app_number] => 12295220 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/295220
Single die MEMS acoustic transducer and manufacturing method Mar 28, 2007 Issued
Array ( [id] => 185946 [patent_doc_number] => 07646033 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-12 [patent_title] => 'Systems and methods for producing white-light light emitting diodes' [patent_app_type] => utility [patent_app_number] => 11/692015 [patent_app_country] => US [patent_app_date] => 2007-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3415 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/646/07646033.pdf [firstpage_image] =>[orig_patent_app_number] => 11692015 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/692015
Systems and methods for producing white-light light emitting diodes Mar 26, 2007 Issued
Array ( [id] => 5188545 [patent_doc_number] => 20070166853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'LED Arrangement' [patent_app_type] => utility [patent_app_number] => 11/686525 [patent_app_country] => US [patent_app_date] => 2007-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4157 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20070166853.pdf [firstpage_image] =>[orig_patent_app_number] => 11686525 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/686525
LED arrangement Mar 14, 2007 Issued
Array ( [id] => 5584536 [patent_doc_number] => 20090103738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-23 [patent_title] => 'Method for Binaural Synthesis Taking Into Account a Room Effect' [patent_app_type] => utility [patent_app_number] => 12/225691 [patent_app_country] => US [patent_app_date] => 2007-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6193 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20090103738.pdf [firstpage_image] =>[orig_patent_app_number] => 12225691 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/225691
Method for binaural synthesis taking into account a room effect Mar 7, 2007 Issued
Array ( [id] => 5498873 [patent_doc_number] => 20090159561 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-25 [patent_title] => 'INTEGRATED DEVICE TECHNOLOGY USING A BURIED POWER BUSS FOR MAJOR DEVICE AND CIRCUIT ADVANTAGES' [patent_app_type] => utility [patent_app_number] => 11/672195 [patent_app_country] => US [patent_app_date] => 2007-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7333 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20090159561.pdf [firstpage_image] =>[orig_patent_app_number] => 11672195 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/672195
INTEGRATED DEVICE TECHNOLOGY USING A BURIED POWER BUSS FOR MAJOR DEVICE AND CIRCUIT ADVANTAGES Feb 6, 2007 Abandoned
Array ( [id] => 5095661 [patent_doc_number] => 20070117270 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-24 [patent_title] => 'INTEGRATED HEAT SPREADER WITH INTERMETALLIC LAYER AND METHOD FOR MAKING' [patent_app_type] => utility [patent_app_number] => 11/625416 [patent_app_country] => US [patent_app_date] => 2007-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3546 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20070117270.pdf [firstpage_image] =>[orig_patent_app_number] => 11625416 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/625416
Integrated heat spreader with intermetallic layer and method for making Jan 21, 2007 Issued
Array ( [id] => 5095695 [patent_doc_number] => 20070117304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-24 [patent_title] => 'METHOD FOR PATTERNING HFO2-CONTAINING DIELECTRIC' [patent_app_type] => utility [patent_app_number] => 11/624703 [patent_app_country] => US [patent_app_date] => 2007-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1876 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20070117304.pdf [firstpage_image] =>[orig_patent_app_number] => 11624703 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/624703
METHOD FOR PATTERNING HFO2-CONTAINING DIELECTRIC Jan 18, 2007 Abandoned
Array ( [id] => 5175119 [patent_doc_number] => 20070176177 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-02 [patent_title] => 'ORGANIC ELECTROLUMINESCENT DISPLAY AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/624273 [patent_app_country] => US [patent_app_date] => 2007-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4908 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20070176177.pdf [firstpage_image] =>[orig_patent_app_number] => 11624273 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/624273
Organic electroluminescent display and method of fabricating the same Jan 17, 2007 Issued
Array ( [id] => 836923 [patent_doc_number] => 07393738 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-07-01 [patent_title] => 'Subground rule STI fill for hot structure' [patent_app_type] => utility [patent_app_number] => 11/623404 [patent_app_country] => US [patent_app_date] => 2007-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 5203 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/393/07393738.pdf [firstpage_image] =>[orig_patent_app_number] => 11623404 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/623404
Subground rule STI fill for hot structure Jan 15, 2007 Issued
Array ( [id] => 239508 [patent_doc_number] => 07592225 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-22 [patent_title] => 'Methods of forming spacer patterns using assist layer for high density semiconductor devices' [patent_app_type] => utility [patent_app_number] => 11/623314 [patent_app_country] => US [patent_app_date] => 2007-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 6813 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/592/07592225.pdf [firstpage_image] =>[orig_patent_app_number] => 11623314 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/623314
Methods of forming spacer patterns using assist layer for high density semiconductor devices Jan 14, 2007 Issued
Array ( [id] => 5092926 [patent_doc_number] => 20070114535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-24 [patent_title] => 'Thin Film Transistor, Thin Film Transistor Substrate, and Methods for Manufacturing the Same' [patent_app_type] => utility [patent_app_number] => 11/623214 [patent_app_country] => US [patent_app_date] => 2007-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3880 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0114/20070114535.pdf [firstpage_image] =>[orig_patent_app_number] => 11623214 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/623214
Thin film transistor, thin film transistor substrate, and methods for manufacturing the same Jan 14, 2007 Issued
Array ( [id] => 4748276 [patent_doc_number] => 20080156346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'METHOD AND APPARATUS FOR CLEANING A SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 11/616964 [patent_app_country] => US [patent_app_date] => 2006-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4163 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20080156346.pdf [firstpage_image] =>[orig_patent_app_number] => 11616964 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/616964
METHOD AND APPARATUS FOR CLEANING A SUBSTRATE Dec 27, 2006 Abandoned
Array ( [id] => 4749218 [patent_doc_number] => 20080157289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'METHOD TO ACHIEVE A LOW COST TRANSISTOR ISOLATION DIELECTRIC PROCESS MODULE WITH IMPROVED PROCESS CONTROL, PROCESS COST, AND YIELD POTENTIAL' [patent_app_type] => utility [patent_app_number] => 11/616384 [patent_app_country] => US [patent_app_date] => 2006-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5878 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20080157289.pdf [firstpage_image] =>[orig_patent_app_number] => 11616384 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/616384
METHOD TO ACHIEVE A LOW COST TRANSISTOR ISOLATION DIELECTRIC PROCESS MODULE WITH IMPROVED PROCESS CONTROL, PROCESS COST, AND YIELD POTENTIAL Dec 26, 2006 Abandoned
Array ( [id] => 5432025 [patent_doc_number] => 20090166611 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'Organic Transistor and Manufacturing Method Thereof' [patent_app_type] => utility [patent_app_number] => 12/224492 [patent_app_country] => US [patent_app_date] => 2006-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5199 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20090166611.pdf [firstpage_image] =>[orig_patent_app_number] => 12224492 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/224492
Organic transistor and manufacturing method thereof Dec 26, 2006 Issued
Array ( [id] => 5219214 [patent_doc_number] => 20070160525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-12 [patent_title] => 'METHOD FOR PRODUCING FINE-GRAINED PARTICLES' [patent_app_type] => utility [patent_app_number] => 11/615424 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 7903 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20070160525.pdf [firstpage_image] =>[orig_patent_app_number] => 11615424 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/615424
Method for producing fine-grained particles Dec 21, 2006 Issued
Array ( [id] => 7751324 [patent_doc_number] => 08110412 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-07 [patent_title] => 'Integrated circuit wafer system with control strategy' [patent_app_type] => utility [patent_app_number] => 11/615583 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 3587 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/110/08110412.pdf [firstpage_image] =>[orig_patent_app_number] => 11615583 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/615583
Integrated circuit wafer system with control strategy Dec 21, 2006 Issued
Array ( [id] => 5022456 [patent_doc_number] => 20070148422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Semiconductor Wafer Substrate For Power Semiconductor Components And Method For Producing The Same' [patent_app_type] => utility [patent_app_number] => 11/613253 [patent_app_country] => US [patent_app_date] => 2006-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5323 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20070148422.pdf [firstpage_image] =>[orig_patent_app_number] => 11613253 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/613253
Semiconductor wafer substrate for power semiconductor components and method for producing the same Dec 19, 2006 Issued
Array ( [id] => 7592923 [patent_doc_number] => 07652278 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-26 [patent_title] => 'Programmable via structure and method of fabricating same' [patent_app_type] => utility [patent_app_number] => 11/612631 [patent_app_country] => US [patent_app_date] => 2006-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 4195 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/652/07652278.pdf [firstpage_image] =>[orig_patent_app_number] => 11612631 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/612631
Programmable via structure and method of fabricating same Dec 18, 2006 Issued
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