Search

Lalrinfamkim Hmar Malsawma

Examiner (ID: 5479)

Most Active Art Unit
2892
Art Unit(s)
2825, 2892, 2823
Total Applications
2001
Issued Applications
1735
Pending Applications
112
Abandoned Applications
179

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5851224 [patent_doc_number] => 20060234415 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-19 [patent_title] => 'Solid state imaging apparatus and driving method of solid state imaging apparatus' [patent_app_type] => utility [patent_app_number] => 11/389177 [patent_app_country] => US [patent_app_date] => 2006-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6950 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0234/20060234415.pdf [firstpage_image] =>[orig_patent_app_number] => 11389177 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/389177
Solid state imaging apparatus and driving method of solid state imaging apparatus Mar 26, 2006 Issued
Array ( [id] => 411511 [patent_doc_number] => 07282391 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-10-16 [patent_title] => 'Method for precision assembly of integrated circuit chip packages' [patent_app_type] => utility [patent_app_number] => 11/385121 [patent_app_country] => US [patent_app_date] => 2006-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 27 [patent_no_of_words] => 4585 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/282/07282391.pdf [firstpage_image] =>[orig_patent_app_number] => 11385121 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/385121
Method for precision assembly of integrated circuit chip packages Mar 20, 2006 Issued
Array ( [id] => 576116 [patent_doc_number] => 07456043 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-25 [patent_title] => 'Method of fabricating microphone device and thermal oxide layer and low-stress structural layer thereof' [patent_app_type] => utility [patent_app_number] => 11/308283 [patent_app_country] => US [patent_app_date] => 2006-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 2170 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/456/07456043.pdf [firstpage_image] =>[orig_patent_app_number] => 11308283 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/308283
Method of fabricating microphone device and thermal oxide layer and low-stress structural layer thereof Mar 14, 2006 Issued
Array ( [id] => 326516 [patent_doc_number] => 07514287 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-07 [patent_title] => 'Method of forming a cavity by two-step etching and method of reducing dimension of a MEMS device' [patent_app_type] => utility [patent_app_number] => 11/308303 [patent_app_country] => US [patent_app_date] => 2006-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1504 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/514/07514287.pdf [firstpage_image] =>[orig_patent_app_number] => 11308303 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/308303
Method of forming a cavity by two-step etching and method of reducing dimension of a MEMS device Mar 14, 2006 Issued
Array ( [id] => 5667114 [patent_doc_number] => 20060172464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-03 [patent_title] => 'Method of embedding semiconductor element in carrier and embedded structure thereof' [patent_app_type] => utility [patent_app_number] => 11/372113 [patent_app_country] => US [patent_app_date] => 2006-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3919 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20060172464.pdf [firstpage_image] =>[orig_patent_app_number] => 11372113 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/372113
Method of embedding semiconductor element in carrier and embedded structure thereof Mar 9, 2006 Abandoned
Array ( [id] => 5154439 [patent_doc_number] => 20070037322 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-15 [patent_title] => 'End electrode structure of a surface-mounted resettable over-current protection device' [patent_app_type] => utility [patent_app_number] => 11/373787 [patent_app_country] => US [patent_app_date] => 2006-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1252 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20070037322.pdf [firstpage_image] =>[orig_patent_app_number] => 11373787 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/373787
End electrode structure of a surface-mounted resettable over-current protection device Mar 9, 2006 Abandoned
Array ( [id] => 5259198 [patent_doc_number] => 20070212830 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-13 [patent_title] => 'TRENCH MEMORY WITH MONOLITHIC CONDUCTING MATERIAL AND METHODS FOR FORMING SAME' [patent_app_type] => utility [patent_app_number] => 11/308103 [patent_app_country] => US [patent_app_date] => 2006-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 2647 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20070212830.pdf [firstpage_image] =>[orig_patent_app_number] => 11308103 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/308103
Trench memory with monolithic conducting material and methods for forming same Mar 6, 2006 Issued
Array ( [id] => 5628801 [patent_doc_number] => 20060145269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Semiconductor device having a capping layer including cobalt and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/365063 [patent_app_country] => US [patent_app_date] => 2006-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3351 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20060145269.pdf [firstpage_image] =>[orig_patent_app_number] => 11365063 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/365063
Semiconductor device having a capping layer including cobalt and method of fabricating the same Feb 27, 2006 Abandoned
Array ( [id] => 5656029 [patent_doc_number] => 20060141765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Metal wiring pattern for memory devices' [patent_app_type] => utility [patent_app_number] => 11/359467 [patent_app_country] => US [patent_app_date] => 2006-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 6582 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20060141765.pdf [firstpage_image] =>[orig_patent_app_number] => 11359467 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/359467
Metal wiring pattern for memory devices Feb 22, 2006 Abandoned
Array ( [id] => 5038171 [patent_doc_number] => 20070090453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-26 [patent_title] => 'NON-VOLATILE MEMORY AND MANUFACTURING METHOD AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 11/307804 [patent_app_country] => US [patent_app_date] => 2006-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7379 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20070090453.pdf [firstpage_image] =>[orig_patent_app_number] => 11307804 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/307804
NON-VOLATILE MEMORY AND MANUFACTURING METHOD AND OPERATING METHOD THEREOF Feb 22, 2006 Abandoned
Array ( [id] => 5113094 [patent_doc_number] => 20070197009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'Method for improving self-aligned silicide extendibility with spacer recess using an aggregated spacer recess etch (ASRE) integration' [patent_app_type] => utility [patent_app_number] => 11/360897 [patent_app_country] => US [patent_app_date] => 2006-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3474 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20070197009.pdf [firstpage_image] =>[orig_patent_app_number] => 11360897 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/360897
Method for improving self-aligned silicide extendibility with spacer recess using an aggregated spacer recess etch (ASRE) integration Feb 21, 2006 Issued
Array ( [id] => 259948 [patent_doc_number] => 07572673 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-11 [patent_title] => 'Wafer level package having a stress relief spacer and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/355545 [patent_app_country] => US [patent_app_date] => 2006-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 6895 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/572/07572673.pdf [firstpage_image] =>[orig_patent_app_number] => 11355545 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/355545
Wafer level package having a stress relief spacer and manufacturing method thereof Feb 14, 2006 Issued
Array ( [id] => 5913018 [patent_doc_number] => 20060128080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-15 [patent_title] => 'Manufacturing method of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/349080 [patent_app_country] => US [patent_app_date] => 2006-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9837 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20060128080.pdf [firstpage_image] =>[orig_patent_app_number] => 11349080 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/349080
Manufacturing method of semiconductor device Feb 7, 2006 Issued
Array ( [id] => 864462 [patent_doc_number] => 07368306 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-06 [patent_title] => 'Field emission device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/347283 [patent_app_country] => US [patent_app_date] => 2006-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 72 [patent_no_of_words] => 22415 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/368/07368306.pdf [firstpage_image] =>[orig_patent_app_number] => 11347283 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/347283
Field emission device and manufacturing method thereof Feb 5, 2006 Issued
Array ( [id] => 826783 [patent_doc_number] => 07402447 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-22 [patent_title] => 'Semiconductor laser device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/346373 [patent_app_country] => US [patent_app_date] => 2006-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 9420 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/402/07402447.pdf [firstpage_image] =>[orig_patent_app_number] => 11346373 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/346373
Semiconductor laser device and method for fabricating the same Feb 2, 2006 Issued
Array ( [id] => 5652690 [patent_doc_number] => 20060138425 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Methods of forming semiconductor constructions' [patent_app_type] => utility [patent_app_number] => 11/346963 [patent_app_country] => US [patent_app_date] => 2006-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9308 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20060138425.pdf [firstpage_image] =>[orig_patent_app_number] => 11346963 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/346963
Methods of forming semiconductor constructions Feb 2, 2006 Issued
Array ( [id] => 5101392 [patent_doc_number] => 20070184654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-09 [patent_title] => 'Methods for fabricating and filling conductive vias and conductive vias so formed' [patent_app_type] => utility [patent_app_number] => 11/347153 [patent_app_country] => US [patent_app_date] => 2006-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10274 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20070184654.pdf [firstpage_image] =>[orig_patent_app_number] => 11347153 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/347153
Methods for fabricating and filling conductive vias and conductive vias so formed Feb 2, 2006 Issued
Array ( [id] => 5652926 [patent_doc_number] => 20060138661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Agglomeration control using early transition metal alloys' [patent_app_type] => utility [patent_app_number] => 11/347051 [patent_app_country] => US [patent_app_date] => 2006-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4354 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20060138661.pdf [firstpage_image] =>[orig_patent_app_number] => 11347051 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/347051
Agglomeration control using early transition metal alloys Feb 2, 2006 Issued
Array ( [id] => 131530 [patent_doc_number] => 07700441 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-20 [patent_title] => 'Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates' [patent_app_type] => utility [patent_app_number] => 11/346914 [patent_app_country] => US [patent_app_date] => 2006-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 4925 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/700/07700441.pdf [firstpage_image] =>[orig_patent_app_number] => 11346914 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/346914
Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates Feb 1, 2006 Issued
Array ( [id] => 5683107 [patent_doc_number] => 20060199377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-07 [patent_title] => 'Method for fabricating a resistively switching nonvolatile memory cell' [patent_app_type] => utility [patent_app_number] => 11/344533 [patent_app_country] => US [patent_app_date] => 2006-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3081 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20060199377.pdf [firstpage_image] =>[orig_patent_app_number] => 11344533 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/344533
Method for fabricating a resistive memory Jan 31, 2006 Issued
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