
Lalrinfamkim Hmar Malsawma
Examiner (ID: 2370)
| Most Active Art Unit | 2892 |
| Art Unit(s) | 2823, 2892, 2825 |
| Total Applications | 1951 |
| Issued Applications | 1709 |
| Pending Applications | 105 |
| Abandoned Applications | 179 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5667114
[patent_doc_number] => 20060172464
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-08-03
[patent_title] => 'Method of embedding semiconductor element in carrier and embedded structure thereof'
[patent_app_type] => utility
[patent_app_number] => 11/372113
[patent_app_country] => US
[patent_app_date] => 2006-03-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3919
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0172/20060172464.pdf
[firstpage_image] =>[orig_patent_app_number] => 11372113
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/372113 | Method of embedding semiconductor element in carrier and embedded structure thereof | Mar 9, 2006 | Abandoned |
Array
(
[id] => 5154439
[patent_doc_number] => 20070037322
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-02-15
[patent_title] => 'End electrode structure of a surface-mounted resettable over-current protection device'
[patent_app_type] => utility
[patent_app_number] => 11/373787
[patent_app_country] => US
[patent_app_date] => 2006-03-10
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 11373787
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/373787 | End electrode structure of a surface-mounted resettable over-current protection device | Mar 9, 2006 | Abandoned |
Array
(
[id] => 5259198
[patent_doc_number] => 20070212830
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-09-13
[patent_title] => 'TRENCH MEMORY WITH MONOLITHIC CONDUCTING MATERIAL AND METHODS FOR FORMING SAME'
[patent_app_type] => utility
[patent_app_number] => 11/308103
[patent_app_country] => US
[patent_app_date] => 2006-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
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[pdf_file] => publications/A1/0212/20070212830.pdf
[firstpage_image] =>[orig_patent_app_number] => 11308103
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/308103 | Trench memory with monolithic conducting material and methods for forming same | Mar 6, 2006 | Issued |
Array
(
[id] => 5628801
[patent_doc_number] => 20060145269
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-06
[patent_title] => 'Semiconductor device having a capping layer including cobalt and method of fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 11/365063
[patent_app_country] => US
[patent_app_date] => 2006-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 3351
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[pdf_file] => publications/A1/0145/20060145269.pdf
[firstpage_image] =>[orig_patent_app_number] => 11365063
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/365063 | Semiconductor device having a capping layer including cobalt and method of fabricating the same | Feb 27, 2006 | Abandoned |
Array
(
[id] => 5656029
[patent_doc_number] => 20060141765
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-29
[patent_title] => 'Metal wiring pattern for memory devices'
[patent_app_type] => utility
[patent_app_number] => 11/359467
[patent_app_country] => US
[patent_app_date] => 2006-02-23
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 11359467
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/359467 | Metal wiring pattern for memory devices | Feb 22, 2006 | Abandoned |
Array
(
[id] => 5038171
[patent_doc_number] => 20070090453
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-04-26
[patent_title] => 'NON-VOLATILE MEMORY AND MANUFACTURING METHOD AND OPERATING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 11/307804
[patent_app_country] => US
[patent_app_date] => 2006-02-23
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/307804 | NON-VOLATILE MEMORY AND MANUFACTURING METHOD AND OPERATING METHOD THEREOF | Feb 22, 2006 | Abandoned |
Array
(
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[patent_doc_number] => 20070197009
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[patent_kind] => A1
[patent_issue_date] => 2007-08-23
[patent_title] => 'Method for improving self-aligned silicide extendibility with spacer recess using an aggregated spacer recess etch (ASRE) integration'
[patent_app_type] => utility
[patent_app_number] => 11/360897
[patent_app_country] => US
[patent_app_date] => 2006-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 3474
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[pdf_file] => publications/A1/0197/20070197009.pdf
[firstpage_image] =>[orig_patent_app_number] => 11360897
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/360897 | Method for improving self-aligned silicide extendibility with spacer recess using an aggregated spacer recess etch (ASRE) integration | Feb 21, 2006 | Issued |
Array
(
[id] => 259948
[patent_doc_number] => 07572673
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-08-11
[patent_title] => 'Wafer level package having a stress relief spacer and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/355545
[patent_app_country] => US
[patent_app_date] => 2006-02-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
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[patent_no_of_words] => 6895
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[pdf_file] => patents/07/572/07572673.pdf
[firstpage_image] =>[orig_patent_app_number] => 11355545
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/355545 | Wafer level package having a stress relief spacer and manufacturing method thereof | Feb 14, 2006 | Issued |
Array
(
[id] => 5913018
[patent_doc_number] => 20060128080
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-15
[patent_title] => 'Manufacturing method of semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/349080
[patent_app_country] => US
[patent_app_date] => 2006-02-08
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[firstpage_image] =>[orig_patent_app_number] => 11349080
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/349080 | Manufacturing method of semiconductor device | Feb 7, 2006 | Issued |
Array
(
[id] => 864462
[patent_doc_number] => 07368306
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-05-06
[patent_title] => 'Field emission device and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/347283
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 11347283
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/347283 | Field emission device and manufacturing method thereof | Feb 5, 2006 | Issued |
Array
(
[id] => 5652926
[patent_doc_number] => 20060138661
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[patent_issue_date] => 2006-06-29
[patent_title] => 'Agglomeration control using early transition metal alloys'
[patent_app_type] => utility
[patent_app_number] => 11/347051
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[firstpage_image] =>[orig_patent_app_number] => 11347051
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/347051 | Agglomeration control using early transition metal alloys | Feb 2, 2006 | Issued |
Array
(
[id] => 5652690
[patent_doc_number] => 20060138425
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[patent_title] => 'Methods of forming semiconductor constructions'
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Array
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[id] => 826783
[patent_doc_number] => 07402447
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[patent_issue_date] => 2008-07-22
[patent_title] => 'Semiconductor laser device and method for fabricating the same'
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Array
(
[id] => 5101392
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[patent_issue_date] => 2007-08-09
[patent_title] => 'Methods for fabricating and filling conductive vias and conductive vias so formed'
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Array
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[patent_title] => 'Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates'
[patent_app_type] => utility
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Array
(
[id] => 5683107
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[patent_issue_date] => 2006-09-07
[patent_title] => 'Method for fabricating a resistively switching nonvolatile memory cell'
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Array
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Array
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[patent_title] => 'Shallow trench filled with two or more dielectrics for isolation and coupling for stress control'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/339874 | Shallow trench filled with two or more dielectrics for isolation and coupling for stress control | Jan 25, 2006 | Issued |