
Lalrinfamkim Hmar Malsawma
Examiner (ID: 2370)
| Most Active Art Unit | 2892 |
| Art Unit(s) | 2823, 2892, 2825 |
| Total Applications | 1951 |
| Issued Applications | 1709 |
| Pending Applications | 105 |
| Abandoned Applications | 179 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 185656
[patent_doc_number] => 07649213
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-01-19
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/234238
[patent_app_country] => US
[patent_app_date] => 2005-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 4388
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 351
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/649/07649213.pdf
[firstpage_image] =>[orig_patent_app_number] => 11234238
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/234238 | Semiconductor device | Sep 25, 2005 | Issued |
Array
(
[id] => 5593855
[patent_doc_number] => 20060157771
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-20
[patent_title] => 'Integrated circuit memory devices and capacitors having carbon nanotube electrodes and methods of forming same'
[patent_app_type] => utility
[patent_app_number] => 11/205253
[patent_app_country] => US
[patent_app_date] => 2005-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4032
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0157/20060157771.pdf
[firstpage_image] =>[orig_patent_app_number] => 11205253
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/205253 | Methods of forming integrated circuit devices having carbon nanotube electrodes therein | Aug 15, 2005 | Issued |
Array
(
[id] => 103151
[patent_doc_number] => 07728432
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-06-01
[patent_title] => 'Narrow and wide copper interconnections composed of (111), (200) and (511) surfaces'
[patent_app_type] => utility
[patent_app_number] => 11/185937
[patent_app_country] => US
[patent_app_date] => 2005-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 31
[patent_no_of_words] => 6904
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/728/07728432.pdf
[firstpage_image] =>[orig_patent_app_number] => 11185937
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/185937 | Narrow and wide copper interconnections composed of (111), (200) and (511) surfaces | Jul 20, 2005 | Issued |
Array
(
[id] => 5239851
[patent_doc_number] => 20070018342
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-01-25
[patent_title] => 'Devices with nanocrystals and methods of formation'
[patent_app_type] => utility
[patent_app_number] => 11/185113
[patent_app_country] => US
[patent_app_date] => 2005-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4689
[patent_no_of_claims] => 90
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0018/20070018342.pdf
[firstpage_image] =>[orig_patent_app_number] => 11185113
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/185113 | Devices with nanocrystals and methods of formation | Jul 19, 2005 | Issued |
Array
(
[id] => 4551975
[patent_doc_number] => 07820553
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-10-26
[patent_title] => 'Prevention of trench photoresist scum'
[patent_app_type] => utility
[patent_app_number] => 11/185047
[patent_app_country] => US
[patent_app_date] => 2005-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 5009
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/820/07820553.pdf
[firstpage_image] =>[orig_patent_app_number] => 11185047
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/185047 | Prevention of trench photoresist scum | Jul 19, 2005 | Issued |
Array
(
[id] => 803284
[patent_doc_number] => 07422988
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-09-09
[patent_title] => 'Rapid detection of imminent failure in laser thermal processing of a substrate'
[patent_app_type] => utility
[patent_app_number] => 11/185454
[patent_app_country] => US
[patent_app_date] => 2005-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 4953
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/422/07422988.pdf
[firstpage_image] =>[orig_patent_app_number] => 11185454
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/185454 | Rapid detection of imminent failure in laser thermal processing of a substrate | Jul 19, 2005 | Issued |
Array
(
[id] => 5820667
[patent_doc_number] => 20060024980
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-02-02
[patent_title] => 'Silica-based film, method of forming the same, composition for forming insulating film for semiconductor device, interconnect structure, and semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/184964
[patent_app_country] => US
[patent_app_date] => 2005-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 17308
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0024/20060024980.pdf
[firstpage_image] =>[orig_patent_app_number] => 11184964
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/184964 | Silica-based film, method of forming the same, composition for forming insulating film for semiconductor device, interconnect structure, and semiconductor device | Jul 19, 2005 | Issued |
Array
(
[id] => 7248140
[patent_doc_number] => 20050272241
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-08
[patent_title] => 'Method for forming interconnects on thin wafers'
[patent_app_type] => utility
[patent_app_number] => 11/184695
[patent_app_country] => US
[patent_app_date] => 2005-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 3580
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0272/20050272241.pdf
[firstpage_image] =>[orig_patent_app_number] => 11184695
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/184695 | Method for forming interconnects on thin wafers | Jul 18, 2005 | Issued |
Array
(
[id] => 813725
[patent_doc_number] => 07413997
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-08-19
[patent_title] => 'Nanostructured electrode'
[patent_app_type] => utility
[patent_app_number] => 11/184463
[patent_app_country] => US
[patent_app_date] => 2005-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 4
[patent_no_of_words] => 2303
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/413/07413997.pdf
[firstpage_image] =>[orig_patent_app_number] => 11184463
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/184463 | Nanostructured electrode | Jul 18, 2005 | Issued |
Array
(
[id] => 5743248
[patent_doc_number] => 20060088973
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-04-27
[patent_title] => 'Methods of fabricating integrated circuit devices having resistors with different resistivities and devices formed thereby'
[patent_app_type] => utility
[patent_app_number] => 11/184413
[patent_app_country] => US
[patent_app_date] => 2005-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3528
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0088/20060088973.pdf
[firstpage_image] =>[orig_patent_app_number] => 11184413
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/184413 | Methods of fabricating integrated circuit devices having resistors with different resistivities therein | Jul 18, 2005 | Issued |
Array
(
[id] => 5602385
[patent_doc_number] => 20060292730
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-12-28
[patent_title] => 'Method and device for CMOS image sensing with separate source formation'
[patent_app_type] => utility
[patent_app_number] => 11/185444
[patent_app_country] => US
[patent_app_date] => 2005-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6490
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0292/20060292730.pdf
[firstpage_image] =>[orig_patent_app_number] => 11185444
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/185444 | Method and device for CMOS image sensing with separate source formation | Jul 18, 2005 | Issued |
Array
(
[id] => 7211465
[patent_doc_number] => 20050252765
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-11-17
[patent_title] => 'Method and apparatus for forming a barrier layer on a substrate'
[patent_app_type] => utility
[patent_app_number] => 11/185214
[patent_app_country] => US
[patent_app_date] => 2005-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6580
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0252/20050252765.pdf
[firstpage_image] =>[orig_patent_app_number] => 11185214
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/185214 | Method and apparatus for forming a barrier layer on a substrate | Jul 18, 2005 | Abandoned |
Array
(
[id] => 7220866
[patent_doc_number] => 20050260774
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-11-24
[patent_title] => 'Method of incorporating magnetic materials in a semiconductor manufacturing process'
[patent_app_type] => utility
[patent_app_number] => 11/182943
[patent_app_country] => US
[patent_app_date] => 2005-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3732
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0260/20050260774.pdf
[firstpage_image] =>[orig_patent_app_number] => 11182943
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/182943 | Method of incorporating magnetic materials in a semiconductor manufacturing process | Jul 17, 2005 | Issued |
Array
(
[id] => 408172
[patent_doc_number] => 07285490
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-10-23
[patent_title] => 'Method for the producing an integrated circuit bar arrangement, in particular comprising a capacitor assembly, in addition to an integrated circuit arrangement'
[patent_app_type] => utility
[patent_app_number] => 11/181574
[patent_app_country] => US
[patent_app_date] => 2005-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 6367
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/285/07285490.pdf
[firstpage_image] =>[orig_patent_app_number] => 11181574
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/181574 | Method for the producing an integrated circuit bar arrangement, in particular comprising a capacitor assembly, in addition to an integrated circuit arrangement | Jul 13, 2005 | Issued |
Array
(
[id] => 7607605
[patent_doc_number] => 07098109
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-08-29
[patent_title] => 'Multi-level memory cell and fabricating method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/160523
[patent_app_country] => US
[patent_app_date] => 2005-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 13
[patent_no_of_words] => 3809
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/098/07098109.pdf
[firstpage_image] =>[orig_patent_app_number] => 11160523
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/160523 | Multi-level memory cell and fabricating method thereof | Jun 27, 2005 | Issued |
Array
(
[id] => 637801
[patent_doc_number] => 07125753
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-10-24
[patent_title] => 'Self-aligned thin capacitively-coupled thyristor structure'
[patent_app_type] => utility
[patent_app_number] => 11/159738
[patent_app_country] => US
[patent_app_date] => 2005-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 19
[patent_no_of_words] => 5307
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/125/07125753.pdf
[firstpage_image] =>[orig_patent_app_number] => 11159738
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/159738 | Self-aligned thin capacitively-coupled thyristor structure | Jun 22, 2005 | Issued |
Array
(
[id] => 522163
[patent_doc_number] => 07190029
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-03-13
[patent_title] => 'Preventive treatment method for a multilayer semiconductor wafer'
[patent_app_type] => utility
[patent_app_number] => 11/157956
[patent_app_country] => US
[patent_app_date] => 2005-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 3151
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/190/07190029.pdf
[firstpage_image] =>[orig_patent_app_number] => 11157956
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/157956 | Preventive treatment method for a multilayer semiconductor wafer | Jun 21, 2005 | Issued |
Array
(
[id] => 6963820
[patent_doc_number] => 20050230717
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-10-20
[patent_title] => 'Semiconductor device of transistor structure having strained semiconductor layer'
[patent_app_type] => utility
[patent_app_number] => 11/147203
[patent_app_country] => US
[patent_app_date] => 2005-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 26
[patent_no_of_words] => 9415
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0230/20050230717.pdf
[firstpage_image] =>[orig_patent_app_number] => 11147203
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/147203 | Semiconductor device of transistor structure having strained semiconductor layer | Jun 7, 2005 | Issued |
Array
(
[id] => 5767749
[patent_doc_number] => 20050264965
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-01
[patent_title] => 'Semiconductor integrated circuit device and method for fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 11/142379
[patent_app_country] => US
[patent_app_date] => 2005-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 6759
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0264/20050264965.pdf
[firstpage_image] =>[orig_patent_app_number] => 11142379
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/142379 | Semiconductor integrated circuit device and method for fabricating the same | Jun 1, 2005 | Abandoned |
Array
(
[id] => 606355
[patent_doc_number] => 07153720
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-12-26
[patent_title] => 'CMOS image sensor'
[patent_app_type] => utility
[patent_app_number] => 11/142783
[patent_app_country] => US
[patent_app_date] => 2005-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 28
[patent_no_of_words] => 9149
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 21
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/153/07153720.pdf
[firstpage_image] =>[orig_patent_app_number] => 11142783
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/142783 | CMOS image sensor | May 31, 2005 | Issued |