
Lalrinfamkim Hmar Malsawma
Examiner (ID: 2370)
| Most Active Art Unit | 2892 |
| Art Unit(s) | 2823, 2892, 2825 |
| Total Applications | 1951 |
| Issued Applications | 1709 |
| Pending Applications | 105 |
| Abandoned Applications | 179 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 447585
[patent_doc_number] => 07253441
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-08-07
[patent_title] => 'Method of manufacturing thin film transistor'
[patent_app_type] => utility
[patent_app_number] => 11/051005
[patent_app_country] => US
[patent_app_date] => 2005-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 48
[patent_no_of_words] => 11758
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/253/07253441.pdf
[firstpage_image] =>[orig_patent_app_number] => 11051005
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/051005 | Method of manufacturing thin film transistor | Feb 3, 2005 | Issued |
Array
(
[id] => 5588832
[patent_doc_number] => 20060038283
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-02-23
[patent_title] => 'Integrated circuit with increased heat transfer'
[patent_app_type] => utility
[patent_app_number] => 11/050572
[patent_app_country] => US
[patent_app_date] => 2005-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3201
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0038/20060038283.pdf
[firstpage_image] =>[orig_patent_app_number] => 11050572
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/050572 | Integrated circuit with increased heat transfer | Feb 2, 2005 | Issued |
Array
(
[id] => 7597734
[patent_doc_number] => 07618843
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-11-17
[patent_title] => 'Method of fabricating multilayer ceramic substrate'
[patent_app_type] => utility
[patent_app_number] => 11/048792
[patent_app_country] => US
[patent_app_date] => 2005-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 13
[patent_no_of_words] => 7741
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/618/07618843.pdf
[firstpage_image] =>[orig_patent_app_number] => 11048792
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/048792 | Method of fabricating multilayer ceramic substrate | Feb 2, 2005 | Issued |
Array
(
[id] => 452925
[patent_doc_number] => 07247523
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-07-24
[patent_title] => 'Two-sided wafer escape package'
[patent_app_type] => utility
[patent_app_number] => 11/047848
[patent_app_country] => US
[patent_app_date] => 2005-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 35
[patent_no_of_words] => 17078
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 216
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/247/07247523.pdf
[firstpage_image] =>[orig_patent_app_number] => 11047848
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/047848 | Two-sided wafer escape package | Jan 30, 2005 | Issued |
Array
(
[id] => 547471
[patent_doc_number] => 07166888
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-01-23
[patent_title] => 'Scalable high density non-volatile memory cells in a contactless memory array'
[patent_app_type] => utility
[patent_app_number] => 11/044703
[patent_app_country] => US
[patent_app_date] => 2005-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 4795
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/166/07166888.pdf
[firstpage_image] =>[orig_patent_app_number] => 11044703
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/044703 | Scalable high density non-volatile memory cells in a contactless memory array | Jan 26, 2005 | Issued |
Array
(
[id] => 5874516
[patent_doc_number] => 20060166424
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-27
[patent_title] => 'Metal gate transistor CMOS process and method for making'
[patent_app_type] => utility
[patent_app_number] => 11/043337
[patent_app_country] => US
[patent_app_date] => 2005-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4557
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0166/20060166424.pdf
[firstpage_image] =>[orig_patent_app_number] => 11043337
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/043337 | Metal gate transistor CMOS process and method for making | Jan 25, 2005 | Issued |
Array
(
[id] => 7236567
[patent_doc_number] => 20050139980
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-30
[patent_title] => 'High density integrated circuit module'
[patent_app_type] => utility
[patent_app_number] => 11/040564
[patent_app_country] => US
[patent_app_date] => 2005-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4097
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0139/20050139980.pdf
[firstpage_image] =>[orig_patent_app_number] => 11040564
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/040564 | High density integrated circuit module | Jan 20, 2005 | Abandoned |
Array
(
[id] => 7185747
[patent_doc_number] => 20050191863
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-01
[patent_title] => 'Semiconductor device contamination reduction in a fluorinated oxide deposition process'
[patent_app_type] => utility
[patent_app_number] => 11/039354
[patent_app_country] => US
[patent_app_date] => 2005-01-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 2359
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0191/20050191863.pdf
[firstpage_image] =>[orig_patent_app_number] => 11039354
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/039354 | Semiconductor device contamination reduction in a fluorinated oxide deposition process | Jan 19, 2005 | Abandoned |
Array
(
[id] => 5593872
[patent_doc_number] => 20060157788
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-20
[patent_title] => 'SRAM memories and microprocessors having logic portions implemented in high-performance silicon substrates and SRAM array portions having field effect transistors with linked bodies and methods for making same'
[patent_app_type] => utility
[patent_app_number] => 11/038593
[patent_app_country] => US
[patent_app_date] => 2005-01-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 8540
[patent_no_of_claims] => 60
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0157/20060157788.pdf
[firstpage_image] =>[orig_patent_app_number] => 11038593
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/038593 | SRAM memories and microprocessors having logic portions implemented in high-performance silicon substrates and SRAM array portions having field effect transistors with linked bodies and method for making same | Jan 18, 2005 | Issued |
Array
(
[id] => 7132854
[patent_doc_number] => 20050179068
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-18
[patent_title] => 'Integrated semiconductor circuit having a logic and power metallization without intermetal dielectric'
[patent_app_type] => utility
[patent_app_number] => 11/037273
[patent_app_country] => US
[patent_app_date] => 2005-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5445
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0179/20050179068.pdf
[firstpage_image] =>[orig_patent_app_number] => 11037273
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/037273 | Integrated semiconductor circuit having a logic and power metallization without intermetal dielectric | Jan 17, 2005 | Issued |
Array
(
[id] => 509480
[patent_doc_number] => 07195944
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-03-27
[patent_title] => 'Systems and methods for producing white-light emitting diodes'
[patent_app_type] => utility
[patent_app_number] => 11/032853
[patent_app_country] => US
[patent_app_date] => 2005-01-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 3378
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/195/07195944.pdf
[firstpage_image] =>[orig_patent_app_number] => 11032853
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/032853 | Systems and methods for producing white-light emitting diodes | Jan 10, 2005 | Issued |
Array
(
[id] => 5628796
[patent_doc_number] => 20060145264
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-06
[patent_title] => 'Stressed field effect transistors on hybrid orientation substrate'
[patent_app_type] => utility
[patent_app_number] => 11/029797
[patent_app_country] => US
[patent_app_date] => 2005-01-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5194
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0145/20060145264.pdf
[firstpage_image] =>[orig_patent_app_number] => 11029797
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/029797 | Stressed field effect transistors on hybrid orientation substrate | Jan 4, 2005 | Issued |
Array
(
[id] => 7253541
[patent_doc_number] => 20050142786
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-30
[patent_title] => 'Methods of fabricating lateral double-diffused metal oxide semiconductor devices'
[patent_app_type] => utility
[patent_app_number] => 11/026424
[patent_app_country] => US
[patent_app_date] => 2004-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1606
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0142/20050142786.pdf
[firstpage_image] =>[orig_patent_app_number] => 11026424
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/026424 | Methods of fabricating lateral double-diffused metal oxide semiconductor devices | Dec 29, 2004 | Issued |
Array
(
[id] => 7253416
[patent_doc_number] => 20050142761
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-30
[patent_title] => 'Method of fabricating split gate flash memory device'
[patent_app_type] => utility
[patent_app_number] => 11/024724
[patent_app_country] => US
[patent_app_date] => 2004-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2965
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0142/20050142761.pdf
[firstpage_image] =>[orig_patent_app_number] => 11024724
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/024724 | Method of fabricating split gate flash memory device | Dec 29, 2004 | Issued |
Array
(
[id] => 630377
[patent_doc_number] => 07132337
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-11-07
[patent_title] => 'Charge-trapping memory device and method of production'
[patent_app_type] => utility
[patent_app_number] => 11/017194
[patent_app_country] => US
[patent_app_date] => 2004-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 2324
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/132/07132337.pdf
[firstpage_image] =>[orig_patent_app_number] => 11017194
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/017194 | Charge-trapping memory device and method of production | Dec 19, 2004 | Issued |
Array
(
[id] => 658055
[patent_doc_number] => 07105370
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-09-12
[patent_title] => 'Method for fabricating a radiation-emitting semiconductor chip based on III-V nitride semiconductor'
[patent_app_type] => utility
[patent_app_number] => 11/017615
[patent_app_country] => US
[patent_app_date] => 2004-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 11
[patent_no_of_words] => 4660
[patent_no_of_claims] => 38
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/105/07105370.pdf
[firstpage_image] =>[orig_patent_app_number] => 11017615
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/017615 | Method for fabricating a radiation-emitting semiconductor chip based on III-V nitride semiconductor | Dec 19, 2004 | Issued |
Array
(
[id] => 7214276
[patent_doc_number] => 20050253223
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-11-17
[patent_title] => 'Semiconductor integrated circuit including metal mesh structure'
[patent_app_type] => utility
[patent_app_number] => 11/014143
[patent_app_country] => US
[patent_app_date] => 2004-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4100
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0253/20050253223.pdf
[firstpage_image] =>[orig_patent_app_number] => 11014143
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/014143 | Semiconductor integrated circuit including metal mesh structure | Dec 15, 2004 | Issued |
Array
(
[id] => 6994111
[patent_doc_number] => 20050133887
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-23
[patent_title] => 'Semiconductor component comprising areas with a high platinum concentration'
[patent_app_type] => utility
[patent_app_number] => 11/014614
[patent_app_country] => US
[patent_app_date] => 2004-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2561
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0133/20050133887.pdf
[firstpage_image] =>[orig_patent_app_number] => 11014614
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/014614 | Semiconductor component comprising areas with a high platinum concentration | Dec 15, 2004 | Issued |
Array
(
[id] => 519424
[patent_doc_number] => 07193262
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-03-20
[patent_title] => 'Low-cost deep trench decoupling capacitor device and process of manufacture'
[patent_app_type] => utility
[patent_app_number] => 10/905094
[patent_app_country] => US
[patent_app_date] => 2004-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 51
[patent_no_of_words] => 7406
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/193/07193262.pdf
[firstpage_image] =>[orig_patent_app_number] => 10905094
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/905094 | Low-cost deep trench decoupling capacitor device and process of manufacture | Dec 14, 2004 | Issued |
Array
(
[id] => 8625101
[patent_doc_number] => 08357595
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-01-22
[patent_title] => 'Semiconductor substrate with solid phase epitaxial regrowth with reduced depth of doping profile and method of producing same'
[patent_app_type] => utility
[patent_app_number] => 10/596603
[patent_app_country] => US
[patent_app_date] => 2004-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 9
[patent_no_of_words] => 2519
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 10596603
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/596603 | Semiconductor substrate with solid phase epitaxial regrowth with reduced depth of doping profile and method of producing same | Dec 9, 2004 | Issued |