Lalrinfamkim Hmar Malsawma

Array ( [id] => 958751 [patent_doc_number] => 06953696 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-11 [patent_title] => 'Method for fabricating semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 10/959972 [patent_app_country] => US [patent_app_date] => 2004-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 5059 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/953/06953696.pdf [firstpage_image] =>[orig_patent_app_number] => 10959972 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7140176 [patent_doc_number] => 20050116326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-02 [patent_title] => 'Formation of circuitry with modification of feature height' [patent_app_type] => utility [patent_app_number] => 10/959465 [patent_app_country] => US [patent_app_date] => 2004-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7127 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20050116326.pdf [firstpage_image] =>[orig_patent_app_number] => 10959465 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 540260 [patent_doc_number] => 07176575 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-13 [patent_title] => 'Input/output routing on an electronic device' [patent_app_type] => utility [patent_app_number] => 10/955944 [patent_app_country] => US [patent_app_date] => 2004-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 6930 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/176/07176575.pdf [firstpage_image] =>[orig_patent_app_number] => 10955944 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 465281 [patent_doc_number] => 07239004 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-03 [patent_title] => 'Semiconductor device having fuse and capacitor at the same level and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 10/946343 [patent_app_country] => US [patent_app_date] => 2004-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5897 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/239/07239004.pdf [firstpage_image] =>[orig_patent_app_number] => 10946343 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7008429 [patent_doc_number] => 20050062145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-24 [patent_title] => 'Land pattern configuration' [patent_app_type] => utility [patent_app_number] => 10/944803 [patent_app_country] => US [patent_app_date] => 2004-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3837 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20050062145.pdf [firstpage_image] =>[orig_patent_app_number] => 10944803 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 616351 [patent_doc_number] => 07144762 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-05 [patent_title] => 'Semiconductor device with pins and method of assembling the semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/941943 [patent_app_country] => US [patent_app_date] => 2004-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 3064 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/144/07144762.pdf [firstpage_image] =>[orig_patent_app_number] => 10941943 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5724264 [patent_doc_number] => 20060055024 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-16 [patent_title] => 'Adapted leaded integrated circuit module' [patent_app_type] => utility [patent_app_number] => 10/940074 [patent_app_country] => US [patent_app_date] => 2004-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3263 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20060055024.pdf [firstpage_image] =>[orig_patent_app_number] => 10940074 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5724303 [patent_doc_number] => 20060055063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-16 [patent_title] => 'Leadframe designs for plastic overmold packages' [patent_app_type] => utility [patent_app_number] => 10/939763 [patent_app_country] => US [patent_app_date] => 2004-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3125 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20060055063.pdf [firstpage_image] =>[orig_patent_app_number] => 10939763 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 45205 [patent_doc_number] => 07777338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-17 [patent_title] => 'Seal ring structure for integrated circuit chips' [patent_app_type] => utility [patent_app_number] => 10/940504 [patent_app_country] => US [patent_app_date] => 2004-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 3646 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/777/07777338.pdf [firstpage_image] =>[orig_patent_app_number] => 10940504 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 564204 [patent_doc_number] => 07157800 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-02 [patent_title] => 'Bonded structure using conductive adhesives, and a manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 10/936503 [patent_app_country] => US [patent_app_date] => 2004-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 7027 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/157/07157800.pdf [firstpage_image] =>[orig_patent_app_number] => 10936503 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 662324 [patent_doc_number] => 07101620 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-09-05 [patent_title] => 'Thermal release wafer mount tape with B-stage adhesive' [patent_app_type] => utility [patent_app_number] => 10/935883 [patent_app_country] => US [patent_app_date] => 2004-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5074 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/101/07101620.pdf [firstpage_image] =>[orig_patent_app_number] => 10935883 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 651295 [patent_doc_number] => 07112873 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-26 [patent_title] => 'Flip chip metal bonding to plastic leadframe' [patent_app_type] => utility [patent_app_number] => 10/934813 [patent_app_country] => US [patent_app_date] => 2004-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2662 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/112/07112873.pdf [firstpage_image] =>[orig_patent_app_number] => 10934813 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5898307 [patent_doc_number] => 20060043540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Silicon package for piezoelectric device' [patent_app_type] => utility [patent_app_number] => 10/931663 [patent_app_country] => US [patent_app_date] => 2004-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2379 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20060043540.pdf [firstpage_image] =>[orig_patent_app_number] => 10931663 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7242011 [patent_doc_number] => 20050073032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-07 [patent_title] => 'Leadless semiconductor package' [patent_app_type] => utility [patent_app_number] => 10/929503 [patent_app_country] => US [patent_app_date] => 2004-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1635 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20050073032.pdf [firstpage_image] =>[orig_patent_app_number] => 10929503 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 540143 [patent_doc_number] => 07176564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-13 [patent_title] => 'Heat spreader, heat sink, heat exchanger and PDP chassis base' [patent_app_type] => utility [patent_app_number] => 10/928893 [patent_app_country] => US [patent_app_date] => 2004-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2012 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/176/07176564.pdf [firstpage_image] =>[orig_patent_app_number] => 10928893 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 353018 [patent_doc_number] => 07492043 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-17 [patent_title] => 'Power module flip chip package' [patent_app_type] => utility [patent_app_number] => 10/927424 [patent_app_country] => US [patent_app_date] => 2004-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2723 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/492/07492043.pdf [firstpage_image] =>[orig_patent_app_number] => 10927424 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 728298 [patent_doc_number] => 07041534 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-09 [patent_title] => 'Semiconductor chip package and method for making the same' [patent_app_type] => utility [patent_app_number] => 10/926334 [patent_app_country] => US [patent_app_date] => 2004-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 5383 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/041/07041534.pdf [firstpage_image] =>[orig_patent_app_number] => 10926334 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 521506 [patent_doc_number] => 07186606 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-06 [patent_title] => 'Method of forming an integrated circuit employable with a power converter' [patent_app_type] => utility [patent_app_number] => 10/924094 [patent_app_country] => US [patent_app_date] => 2004-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 14855 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/186/07186606.pdf [firstpage_image] =>[orig_patent_app_number] => 10924094 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 754337 [patent_doc_number] => 07018904 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-28 [patent_title] => 'Semiconductor chip having multiple functional blocks integrated in a single chip and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 10/921273 [patent_app_country] => US [patent_app_date] => 2004-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 39 [patent_no_of_words] => 13248 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/018/07018904.pdf [firstpage_image] =>[orig_patent_app_number] => 10921273 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7169192 [patent_doc_number] => 20050121765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'Multi-chips bumpless assembly package and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 10/920383 [patent_app_country] => US [patent_app_date] => 2004-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2910 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20050121765.pdf [firstpage_image] =>[orig_patent_app_number] => 10920383 [rel_patent_id] =>[rel_patent_doc_number] =>)