
Lalrinfamkim Hmar Malsawma
Examiner (ID: 2370)
| Most Active Art Unit | 2892 |
| Art Unit(s) | 2823, 2892, 2825 |
| Total Applications | 1951 |
| Issued Applications | 1709 |
| Pending Applications | 105 |
| Abandoned Applications | 179 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7291844
[patent_doc_number] => 20040212082
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-28
[patent_title] => 'Method to prevent die attach adhesive contamination in stacked chips'
[patent_app_type] => new
[patent_app_number] => 10/852315
[patent_app_country] => US
[patent_app_date] => 2004-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5651
[patent_no_of_claims] => 48
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0212/20040212082.pdf
[firstpage_image] =>[orig_patent_app_number] => 10852315
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/852315 | Plurality of semiconductor die in an assembly | May 23, 2004 | Issued |
Array
(
[id] => 7296607
[patent_doc_number] => 20040214452
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-28
[patent_title] => 'Method for optically trimming electronic components'
[patent_app_type] => new
[patent_app_number] => 10/846210
[patent_app_country] => US
[patent_app_date] => 2004-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4155
[patent_no_of_claims] => 56
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 49
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0214/20040214452.pdf
[firstpage_image] =>[orig_patent_app_number] => 10846210
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/846210 | Method for optically trimming electronic components | May 13, 2004 | Issued |
Array
(
[id] => 7061273
[patent_doc_number] => 20050003634
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-06
[patent_title] => 'Semiconductor device separation using a patterned laser projection'
[patent_app_type] => utility
[patent_app_number] => 10/845790
[patent_app_country] => US
[patent_app_date] => 2004-05-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3553
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0003/20050003634.pdf
[firstpage_image] =>[orig_patent_app_number] => 10845790
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/845790 | Semiconductor device separation using a patterned laser projection | May 12, 2004 | Abandoned |
Array
(
[id] => 7045662
[patent_doc_number] => 20050250257
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-11-10
[patent_title] => 'Method of forming a super-junction semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/841670
[patent_app_country] => US
[patent_app_date] => 2004-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 3768
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0250/20050250257.pdf
[firstpage_image] =>[orig_patent_app_number] => 10841670
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/841670 | Method of forming a super-junction semiconductor device | May 9, 2004 | Issued |
Array
(
[id] => 7045683
[patent_doc_number] => 20050250278
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-11-10
[patent_title] => 'Methods and apparatus for wordline protection in flash memory devices'
[patent_app_type] => utility
[patent_app_number] => 10/839614
[patent_app_country] => US
[patent_app_date] => 2004-05-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 6539
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0250/20050250278.pdf
[firstpage_image] =>[orig_patent_app_number] => 10839614
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/839614 | Methods and apparatus for wordline protection in flash memory devices | May 4, 2004 | Issued |
Array
(
[id] => 7067021
[patent_doc_number] => 20050242403
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-11-03
[patent_title] => 'Isolation trench'
[patent_app_type] => utility
[patent_app_number] => 10/836150
[patent_app_country] => US
[patent_app_date] => 2004-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3382
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0242/20050242403.pdf
[firstpage_image] =>[orig_patent_app_number] => 10836150
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/836150 | Isolation trench | Apr 29, 2004 | Issued |
Array
(
[id] => 1073678
[patent_doc_number] => 06838343
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-01-04
[patent_title] => 'Flash memory with self-aligned split gate and methods for fabricating and for operating the same'
[patent_app_type] => utility
[patent_app_number] => 10/709310
[patent_app_country] => US
[patent_app_date] => 2004-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 16
[patent_no_of_words] => 4854
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 211
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/838/06838343.pdf
[firstpage_image] =>[orig_patent_app_number] => 10709310
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/709310 | Flash memory with self-aligned split gate and methods for fabricating and for operating the same | Apr 27, 2004 | Issued |
Array
(
[id] => 7132947
[patent_doc_number] => 20050179102
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-18
[patent_title] => 'Chip assembly in a premold housing'
[patent_app_type] => utility
[patent_app_number] => 10/832534
[patent_app_country] => US
[patent_app_date] => 2004-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3809
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0179/20050179102.pdf
[firstpage_image] =>[orig_patent_app_number] => 10832534
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/832534 | Chip assembly in a premold housing | Apr 25, 2004 | Issued |
Array
(
[id] => 7620121
[patent_doc_number] => 06943061
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-09-13
[patent_title] => 'Method of fabricating semiconductor chip package using screen printing of epoxy on wafer'
[patent_app_type] => utility
[patent_app_number] => 10/823280
[patent_app_country] => US
[patent_app_date] => 2004-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 31
[patent_no_of_words] => 2869
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/943/06943061.pdf
[firstpage_image] =>[orig_patent_app_number] => 10823280
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/823280 | Method of fabricating semiconductor chip package using screen printing of epoxy on wafer | Apr 11, 2004 | Issued |
Array
(
[id] => 7184084
[patent_doc_number] => 20040203194
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-14
[patent_title] => 'Method of resin-sealing a semiconductor device, resin-sealed semiconductor device, and forming die for resin-sealing the semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/814180
[patent_app_country] => US
[patent_app_date] => 2004-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4694
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0203/20040203194.pdf
[firstpage_image] =>[orig_patent_app_number] => 10814180
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/814180 | Method of resin-sealing a semiconductor device, resin-sealed semiconductor device, and forming die for resin-sealing the semiconductor device | Mar 31, 2004 | Abandoned |
Array
(
[id] => 500438
[patent_doc_number] => 07205228
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-04-17
[patent_title] => 'Selective metal encapsulation schemes'
[patent_app_type] => utility
[patent_app_number] => 10/812480
[patent_app_country] => US
[patent_app_date] => 2004-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 8599
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/205/07205228.pdf
[firstpage_image] =>[orig_patent_app_number] => 10812480
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/812480 | Selective metal encapsulation schemes | Mar 29, 2004 | Issued |
Array
(
[id] => 7398306
[patent_doc_number] => 20040174744
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-09
[patent_title] => 'Non-volatile memory with improved programming and method therefor'
[patent_app_type] => new
[patent_app_number] => 10/804770
[patent_app_country] => US
[patent_app_date] => 2004-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[pdf_file] => publications/A1/0174/20040174744.pdf
[firstpage_image] =>[orig_patent_app_number] => 10804770
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/804770 | Non-volatile memory with improved programming and method therefor | Mar 18, 2004 | Abandoned |
Array
(
[id] => 7328899
[patent_doc_number] => 20040253782
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-16
[patent_title] => 'Transistor and electronic device'
[patent_app_type] => new
[patent_app_number] => 10/804060
[patent_app_country] => US
[patent_app_date] => 2004-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0253/20040253782.pdf
[firstpage_image] =>[orig_patent_app_number] => 10804060
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/804060 | Transistor and electronic device | Mar 18, 2004 | Issued |
Array
(
[id] => 1040535
[patent_doc_number] => 06869833
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-03-22
[patent_title] => 'Method of manufacturing a thin film transistor of a liquid crystal display'
[patent_app_type] => utility
[patent_app_number] => 10/708620
[patent_app_country] => US
[patent_app_date] => 2004-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 2178
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/869/06869833.pdf
[firstpage_image] =>[orig_patent_app_number] => 10708620
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/708620 | Method of manufacturing a thin film transistor of a liquid crystal display | Mar 15, 2004 | Issued |
Array
(
[id] => 7150122
[patent_doc_number] => 20040171204
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-02
[patent_title] => 'Low temperature formation of backside ohmic contacts for vertical devices'
[patent_app_type] => new
[patent_app_number] => 10/799140
[patent_app_country] => US
[patent_app_date] => 2004-03-12
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[pdf_file] => publications/A1/0171/20040171204.pdf
[firstpage_image] =>[orig_patent_app_number] => 10799140
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/799140 | Low temperature formation of backside ohmic contacts for vertical devices | Mar 11, 2004 | Issued |
Array
(
[id] => 7617127
[patent_doc_number] => 06946313
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-09-20
[patent_title] => 'Method of making an aligned electrode on a semiconductor structure'
[patent_app_type] => utility
[patent_app_number] => 10/798770
[patent_app_country] => US
[patent_app_date] => 2004-03-12
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/946/06946313.pdf
[firstpage_image] =>[orig_patent_app_number] => 10798770
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/798770 | Method of making an aligned electrode on a semiconductor structure | Mar 11, 2004 | Issued |
Array
(
[id] => 7185503
[patent_doc_number] => 20050191802
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-01
[patent_title] => 'Method of integrating the formation of a shallow junction N channel device with the formation of P channel, ESD and input/output devices'
[patent_app_type] => utility
[patent_app_number] => 10/788170
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 10788170
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/788170 | Method of integrating the formation of a shallow junction N channel device with the formation of P channel, ESD and input/output devices | Feb 25, 2004 | Issued |
Array
(
[id] => 7462246
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[patent_issue_date] => 2004-10-07
[patent_title] => 'Preventive treatment method for a multilayer semiconductor wafer'
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[firstpage_image] =>[orig_patent_app_number] => 10784040
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/784040 | Preventive treatment method for a multilayer semiconductor wafer | Feb 19, 2004 | Issued |
Array
(
[id] => 7429341
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[patent_issue_date] => 2004-08-19
[patent_title] => 'Method to fabricate an intrinsic polycrystalline silicon film'
[patent_app_type] => new
[patent_app_number] => 10/778440
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 10778440
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/778440 | Method to fabricate an intrinsic polycrystalline silicon film | Feb 12, 2004 | Issued |
Array
(
[id] => 1046789
[patent_doc_number] => 06864184
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[patent_issue_date] => 2005-03-08
[patent_title] => 'Method for reducing critical dimension attainable via the use of an organic conforming layer'
[patent_app_type] => utility
[patent_app_number] => 10/772830
[patent_app_country] => US
[patent_app_date] => 2004-02-05
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 3723
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/864/06864184.pdf
[firstpage_image] =>[orig_patent_app_number] => 10772830
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/772830 | Method for reducing critical dimension attainable via the use of an organic conforming layer | Feb 4, 2004 | Issued |