
Lalrinfamkim Hmar Malsawma
Examiner (ID: 2370)
| Most Active Art Unit | 2892 |
| Art Unit(s) | 2823, 2892, 2825 |
| Total Applications | 1951 |
| Issued Applications | 1709 |
| Pending Applications | 105 |
| Abandoned Applications | 179 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 737182
[patent_doc_number] => 07033906
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-04-25
[patent_title] => 'Airdome enclosure for components'
[patent_app_type] => utility
[patent_app_number] => 10/769935
[patent_app_country] => US
[patent_app_date] => 2004-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1534
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/033/07033906.pdf
[firstpage_image] =>[orig_patent_app_number] => 10769935
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/769935 | Airdome enclosure for components | Feb 1, 2004 | Issued |
Array
(
[id] => 7005285
[patent_doc_number] => 20050170598
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-04
[patent_title] => 'Silicided amorphous polysilicon - metal capacitor'
[patent_app_type] => utility
[patent_app_number] => 10/767390
[patent_app_country] => US
[patent_app_date] => 2004-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 3074
[patent_no_of_claims] => 23
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0170/20050170598.pdf
[firstpage_image] =>[orig_patent_app_number] => 10767390
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/767390 | Silicided amorphous polysilicon - metal capacitor | Jan 28, 2004 | Abandoned |
Array
(
[id] => 985470
[patent_doc_number] => 06924198
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-08-02
[patent_title] => 'Self-aligned trench transistor using etched contact'
[patent_app_type] => utility
[patent_app_number] => 10/767028
[patent_app_country] => US
[patent_app_date] => 2004-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 58
[patent_figures_cnt] => 90
[patent_no_of_words] => 16813
[patent_no_of_claims] => 19
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/924/06924198.pdf
[firstpage_image] =>[orig_patent_app_number] => 10767028
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/767028 | Self-aligned trench transistor using etched contact | Jan 27, 2004 | Issued |
Array
(
[id] => 7296533
[patent_doc_number] => 20040214407
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-28
[patent_title] => 'Semiconductor structures with structural homogeneity'
[patent_app_type] => new
[patent_app_number] => 10/765372
[patent_app_country] => US
[patent_app_date] => 2004-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 9291
[patent_no_of_claims] => 75
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0214/20040214407.pdf
[firstpage_image] =>[orig_patent_app_number] => 10765372
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/765372 | Semiconductor structures with structural homogeneity | Jan 26, 2004 | Issued |
Array
(
[id] => 779172
[patent_doc_number] => 06995039
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-02-07
[patent_title] => 'Method and apparatus for electrostatically aligning integrated circuits'
[patent_app_type] => utility
[patent_app_number] => 10/759923
[patent_app_country] => US
[patent_app_date] => 2004-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 2998
[patent_no_of_claims] => 16
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/995/06995039.pdf
[firstpage_image] =>[orig_patent_app_number] => 10759923
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/759923 | Method and apparatus for electrostatically aligning integrated circuits | Jan 14, 2004 | Issued |
Array
(
[id] => 534681
[patent_doc_number] => 07176128
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-02-13
[patent_title] => 'Method for fabrication of a contact structure'
[patent_app_type] => utility
[patent_app_number] => 10/755844
[patent_app_country] => US
[patent_app_date] => 2004-01-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 13
[patent_no_of_words] => 5040
[patent_no_of_claims] => 23
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[pdf_file] => patents/07/176/07176128.pdf
[firstpage_image] =>[orig_patent_app_number] => 10755844
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/755844 | Method for fabrication of a contact structure | Jan 11, 2004 | Issued |
Array
(
[id] => 972131
[patent_doc_number] => 06936516
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-08-30
[patent_title] => 'Replacement gate strained silicon finFET process'
[patent_app_type] => utility
[patent_app_number] => 10/755811
[patent_app_country] => US
[patent_app_date] => 2004-01-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 14
[patent_no_of_words] => 3858
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/936/06936516.pdf
[firstpage_image] =>[orig_patent_app_number] => 10755811
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/755811 | Replacement gate strained silicon finFET process | Jan 11, 2004 | Issued |
Array
(
[id] => 7235323
[patent_doc_number] => 20040157410
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-08-12
[patent_title] => 'Semiconductor device, semiconductor module, electronic equipment, method for manufacturing semiconductor device, and method for manufacturing semiconductor module'
[patent_app_type] => new
[patent_app_number] => 10/753360
[patent_app_country] => US
[patent_app_date] => 2004-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 9561
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 21
[patent_words_short_claim] => 43
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0157/20040157410.pdf
[firstpage_image] =>[orig_patent_app_number] => 10753360
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/753360 | Semiconductor device, semiconductor module, electronic equipment, method for manufacturing semiconductor device, and method for manufacturing semiconductor module | Jan 8, 2004 | Abandoned |
Array
(
[id] => 646391
[patent_doc_number] => 07119414
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-10-10
[patent_title] => 'Fuse layout and method trimming'
[patent_app_type] => utility
[patent_app_number] => 10/752542
[patent_app_country] => US
[patent_app_date] => 2004-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 3260
[patent_no_of_claims] => 14
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/119/07119414.pdf
[firstpage_image] =>[orig_patent_app_number] => 10752542
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/752542 | Fuse layout and method trimming | Jan 7, 2004 | Issued |
Array
(
[id] => 941270
[patent_doc_number] => 06969661
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-11-29
[patent_title] => 'Method for forming a localized region of a material difficult to etch'
[patent_app_type] => utility
[patent_app_number] => 10/744680
[patent_app_country] => US
[patent_app_date] => 2003-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 10
[patent_no_of_words] => 2851
[patent_no_of_claims] => 9
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/969/06969661.pdf
[firstpage_image] =>[orig_patent_app_number] => 10744680
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/744680 | Method for forming a localized region of a material difficult to etch | Dec 22, 2003 | Issued |
Array
(
[id] => 769106
[patent_doc_number] => 07005356
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-02-28
[patent_title] => 'Schottky barrier transistor and method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 10/746493
[patent_app_country] => US
[patent_app_date] => 2003-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/005/07005356.pdf
[firstpage_image] =>[orig_patent_app_number] => 10746493
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/746493 | Schottky barrier transistor and method of manufacturing the same | Dec 22, 2003 | Issued |
| 10/739590 | Adhesion treatment for OSG-dielectric film adhesion | Dec 17, 2003 | Abandoned |
Array
(
[id] => 1040566
[patent_doc_number] => 06869864
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-03-22
[patent_title] => 'Method for producing quantum dot silicate thin film for light emitting device'
[patent_app_type] => utility
[patent_app_number] => 10/734230
[patent_app_country] => US
[patent_app_date] => 2003-12-15
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/869/06869864.pdf
[firstpage_image] =>[orig_patent_app_number] => 10734230
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/734230 | Method for producing quantum dot silicate thin film for light emitting device | Dec 14, 2003 | Issued |
Array
(
[id] => 7607193
[patent_doc_number] => 07098523
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-08-29
[patent_title] => 'Controlled leakage CMOS decoupling capacitor for application specific integrated circuit libraries'
[patent_app_type] => utility
[patent_app_number] => 10/732950
[patent_app_country] => US
[patent_app_date] => 2003-12-11
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/098/07098523.pdf
[firstpage_image] =>[orig_patent_app_number] => 10732950
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/732950 | Controlled leakage CMOS decoupling capacitor for application specific integrated circuit libraries | Dec 10, 2003 | Issued |
Array
(
[id] => 1021510
[patent_doc_number] => 06887772
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-05-03
[patent_title] => 'Structures of high voltage device and low voltage device, and method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 10/721970
[patent_app_country] => US
[patent_app_date] => 2003-11-24
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[pdf_file] => patents/06/887/06887772.pdf
[firstpage_image] =>[orig_patent_app_number] => 10721970
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/721970 | Structures of high voltage device and low voltage device, and method of manufacturing the same | Nov 23, 2003 | Issued |
Array
(
[id] => 1073693
[patent_doc_number] => 06838358
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-01-04
[patent_title] => 'Method of manufacturing a wafer'
[patent_app_type] => utility
[patent_app_number] => 10/716900
[patent_app_country] => US
[patent_app_date] => 2003-11-18
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[firstpage_image] =>[orig_patent_app_number] => 10716900
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/716900 | Method of manufacturing a wafer | Nov 17, 2003 | Issued |
Array
(
[id] => 542579
[patent_doc_number] => 07166532
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-01-23
[patent_title] => 'Method for forming a contact using a dual damascene process in semiconductor fabrication'
[patent_app_type] => utility
[patent_app_number] => 10/712740
[patent_app_country] => US
[patent_app_date] => 2003-11-13
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[pdf_file] => patents/07/166/07166532.pdf
[firstpage_image] =>[orig_patent_app_number] => 10712740
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/712740 | Method for forming a contact using a dual damascene process in semiconductor fabrication | Nov 12, 2003 | Issued |
Array
(
[id] => 782743
[patent_doc_number] => 06991991
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-01-31
[patent_title] => 'Method for preventing to form a spacer undercut in SEG pre-clean process'
[patent_app_type] => utility
[patent_app_number] => 10/705500
[patent_app_country] => US
[patent_app_date] => 2003-11-12
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[pdf_file] => patents/06/991/06991991.pdf
[firstpage_image] =>[orig_patent_app_number] => 10705500
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/705500 | Method for preventing to form a spacer undercut in SEG pre-clean process | Nov 11, 2003 | Issued |
Array
(
[id] => 7264038
[patent_doc_number] => 20040241926
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-02
[patent_title] => 'Contactless mask progammable rom'
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[patent_app_number] => 10/477880
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[firstpage_image] =>[orig_patent_app_number] => 10477880
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/477880 | Contactless mask progammable rom | Nov 11, 2003 | Abandoned |
Array
(
[id] => 756383
[patent_doc_number] => 07019394
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-03-28
[patent_title] => 'Circuit package and method of plating the same'
[patent_app_type] => utility
[patent_app_number] => 10/674370
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[firstpage_image] =>[orig_patent_app_number] => 10674370
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/674370 | Circuit package and method of plating the same | Sep 29, 2003 | Issued |