Lalrinfamkim Hmar Malsawma

Array ( [id] => 7280879 [patent_doc_number] => 20040063256 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-01 [patent_title] => 'Manufacturing method of semiconductor device' [patent_app_type] => new [patent_app_number] => 10/670310 [patent_app_country] => US [patent_app_date] => 2003-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9957 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20040063256.pdf [firstpage_image] =>[orig_patent_app_number] => 10670310 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 525673 [patent_doc_number] => 07183193 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-27 [patent_title] => 'Integrated device technology using a buried power buss for major device and circuit advantages' [patent_app_type] => utility [patent_app_number] => 10/669762 [patent_app_country] => US [patent_app_date] => 2003-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 7292 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/183/07183193.pdf [firstpage_image] =>[orig_patent_app_number] => 10669762 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7008409 [patent_doc_number] => 20050062125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-24 [patent_title] => 'Lateral short-channel dmos, method of manufacturing the same, and semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/491140 [patent_app_country] => US [patent_app_date] => 2003-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9678 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20050062125.pdf [firstpage_image] =>[orig_patent_app_number] => 10491140 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7280868 [patent_doc_number] => 20040063245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-01 [patent_title] => 'Method of fabricating an electronic component' [patent_app_type] => new [patent_app_number] => 10/663200 [patent_app_country] => US [patent_app_date] => 2003-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6691 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20040063245.pdf [firstpage_image] =>[orig_patent_app_number] => 10663200 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 972123 [patent_doc_number] => 06936508 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-30 [patent_title] => 'Metal gate MOS transistors and methods for making the same' [patent_app_type] => utility [patent_app_number] => 10/661130 [patent_app_country] => US [patent_app_date] => 2003-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 7622 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/936/06936508.pdf [firstpage_image] =>[orig_patent_app_number] => 10661130 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7269993 [patent_doc_number] => 20040058511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-25 [patent_title] => 'Substrate and manufacturing method therefor' [patent_app_type] => new [patent_app_number] => 10/653950 [patent_app_country] => US [patent_app_date] => 2003-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13136 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0058/20040058511.pdf [firstpage_image] =>[orig_patent_app_number] => 10653950 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7083317 [patent_doc_number] => 20050048697 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-03 [patent_title] => 'Self-assembled nanometer conductive bumps and method for fabricating' [patent_app_type] => utility [patent_app_number] => 10/653860 [patent_app_country] => US [patent_app_date] => 2003-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3019 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20050048697.pdf [firstpage_image] =>[orig_patent_app_number] => 10653860 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7328930 [patent_doc_number] => 20040253797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-16 [patent_title] => 'Heating plate crystallization method' [patent_app_type] => new [patent_app_number] => 10/648290 [patent_app_country] => US [patent_app_date] => 2003-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2698 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20040253797.pdf [firstpage_image] =>[orig_patent_app_number] => 10648290 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7609495 [patent_doc_number] => 06998694 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-14 [patent_title] => 'High switching speed two mask Schottky diode with high field breakdown' [patent_app_type] => utility [patent_app_number] => 10/633500 [patent_app_country] => US [patent_app_date] => 2003-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 1971 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/998/06998694.pdf [firstpage_image] =>[orig_patent_app_number] => 10633500 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7400683 [patent_doc_number] => 20040023480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-05 [patent_title] => 'Semiconductor processing methods, and semiconductor assemblies' [patent_app_type] => new [patent_app_number] => 10/630114 [patent_app_country] => US [patent_app_date] => 2003-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2930 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20040023480.pdf [firstpage_image] =>[orig_patent_app_number] => 10630114 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7335563 [patent_doc_number] => 20040132280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-08 [patent_title] => 'Method of forming metal wiring in a semiconductor device' [patent_app_type] => new [patent_app_number] => 10/626550 [patent_app_country] => US [patent_app_date] => 2003-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1485 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20040132280.pdf [firstpage_image] =>[orig_patent_app_number] => 10626550 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7609869 [patent_doc_number] => 06998318 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-14 [patent_title] => 'Method for forming short-channel transistors' [patent_app_type] => utility [patent_app_number] => 10/627300 [patent_app_country] => US [patent_app_date] => 2003-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1563 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/998/06998318.pdf [firstpage_image] =>[orig_patent_app_number] => 10627300 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1014583 [patent_doc_number] => 06893925 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-17 [patent_title] => 'Layout to minimize gate orientation related skew effects' [patent_app_type] => utility [patent_app_number] => 10/624831 [patent_app_country] => US [patent_app_date] => 2003-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 2810 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/893/06893925.pdf [firstpage_image] =>[orig_patent_app_number] => 10624831 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 408130 [patent_doc_number] => 07285447 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-23 [patent_title] => 'Method and apparatus for imprinting a circuit pattern using ultrasonic vibrations' [patent_app_type] => utility [patent_app_number] => 10/607294 [patent_app_country] => US [patent_app_date] => 2003-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 28 [patent_no_of_words] => 7142 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/285/07285447.pdf [firstpage_image] =>[orig_patent_app_number] => 10607294 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 744505 [patent_doc_number] => 07026170 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-11 [patent_title] => 'Methods of controlling optical properties of a capping insulating layer on memory devices, and system for performing same' [patent_app_type] => utility [patent_app_number] => 10/458881 [patent_app_country] => US [patent_app_date] => 2003-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4610 [patent_no_of_claims] => 77 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/026/07026170.pdf [firstpage_image] =>[orig_patent_app_number] => 10458881 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7394941 [patent_doc_number] => 20040038467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-26 [patent_title] => 'Trench MIS device having implanted drain-drift region and thick bottom oxide and process for manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/454031 [patent_app_country] => US [patent_app_date] => 2003-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 9514 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20040038467.pdf [firstpage_image] =>[orig_patent_app_number] => 10454031 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 979025 [patent_doc_number] => 06930030 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-16 [patent_title] => 'Method of forming an electronic device on a recess in the surface of a thin film of silicon etched to a precise thickness' [patent_app_type] => utility [patent_app_number] => 10/453080 [patent_app_country] => US [patent_app_date] => 2003-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 4761 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/930/06930030.pdf [firstpage_image] =>[orig_patent_app_number] => 10453080 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 708591 [patent_doc_number] => 07061023 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-13 [patent_title] => 'Integrated optical devices and methods of making such devices' [patent_app_type] => utility [patent_app_number] => 10/449214 [patent_app_country] => US [patent_app_date] => 2003-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 99 [patent_no_of_words] => 7883 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/061/07061023.pdf [firstpage_image] =>[orig_patent_app_number] => 10449214 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 990724 [patent_doc_number] => 06919250 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-19 [patent_title] => 'Multiple-gate MOS device and method for making the same' [patent_app_type] => utility [patent_app_number] => 10/442131 [patent_app_country] => US [patent_app_date] => 2003-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2306 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/919/06919250.pdf [firstpage_image] =>[orig_patent_app_number] => 10442131 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7490448 [patent_doc_number] => 08030172 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-10-04 [patent_title] => 'Isolation technology for submicron semiconductor devices' [patent_app_type] => utility [patent_app_number] => 10/436411 [patent_app_country] => US [patent_app_date] => 2003-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 13 [patent_no_of_words] => 3662 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/030/08030172.pdf [firstpage_image] =>[orig_patent_app_number] => 10436411 [rel_patent_id] =>[rel_patent_doc_number] =>)