Search

Lalrinfamkim Hmar Malsawma

Examiner (ID: 2370)

Most Active Art Unit
2892
Art Unit(s)
2823, 2892, 2825
Total Applications
1951
Issued Applications
1709
Pending Applications
105
Abandoned Applications
179

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7365773 [patent_doc_number] => 20040005772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-08 [patent_title] => 'Method of producing copper foil solder bump' [patent_app_type] => new [patent_app_number] => 10/434410 [patent_app_country] => US [patent_app_date] => 2003-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2395 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20040005772.pdf [firstpage_image] =>[orig_patent_app_number] => 10434410 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/434410
Method of producing copper foil solder bump May 7, 2003 Abandoned
Array ( [id] => 7274502 [patent_doc_number] => 20040233953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Laser diode having an active layer containing N and operable in a 0.6um wavelength band' [patent_app_type] => new [patent_app_number] => 10/428074 [patent_app_country] => US [patent_app_date] => 2003-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 20107 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20040233953.pdf [firstpage_image] =>[orig_patent_app_number] => 10428074 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/428074
Laser diode having an active layer containing N and operable in a 0.6 μm wavelength band May 1, 2003 Issued
Array ( [id] => 931140 [patent_doc_number] => 06979644 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-27 [patent_title] => 'Method of manufacturing electronic circuit component' [patent_app_type] => utility [patent_app_number] => 10/420751 [patent_app_country] => US [patent_app_date] => 2003-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 30 [patent_no_of_words] => 3938 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/979/06979644.pdf [firstpage_image] =>[orig_patent_app_number] => 10420751 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/420751
Method of manufacturing electronic circuit component Apr 22, 2003 Issued
Array ( [id] => 7405261 [patent_doc_number] => 20040226909 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-18 [patent_title] => 'Reflective spatial light modulator mirror device manufacturing process and layout method' [patent_app_type] => new [patent_app_number] => 10/421200 [patent_app_country] => US [patent_app_date] => 2003-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 1574 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0226/20040226909.pdf [firstpage_image] =>[orig_patent_app_number] => 10421200 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/421200
Reflective spatial light modulator mirror device manufacturing process and layout method Apr 22, 2003 Issued
Array ( [id] => 1024484 [patent_doc_number] => 06884645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-26 [patent_title] => 'Method for preparing a device structure having a wafer structure deposited on a composite substrate having a matched coefficient of thermal expansion' [patent_app_type] => utility [patent_app_number] => 10/418870 [patent_app_country] => US [patent_app_date] => 2003-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4122 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/884/06884645.pdf [firstpage_image] =>[orig_patent_app_number] => 10418870 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/418870
Method for preparing a device structure having a wafer structure deposited on a composite substrate having a matched coefficient of thermal expansion Apr 17, 2003 Issued
Array ( [id] => 6829929 [patent_doc_number] => 20030180987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-25 [patent_title] => 'Stacked die package' [patent_app_type] => new [patent_app_number] => 10/413320 [patent_app_country] => US [patent_app_date] => 2003-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2629 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20030180987.pdf [firstpage_image] =>[orig_patent_app_number] => 10413320 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/413320
Stacked die package Apr 14, 2003 Issued
Array ( [id] => 951290 [patent_doc_number] => 06960492 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-01 [patent_title] => 'Semiconductor device having multilayer wiring and manufacturing method therefor' [patent_app_type] => utility [patent_app_number] => 10/401870 [patent_app_country] => US [patent_app_date] => 2003-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 22 [patent_no_of_words] => 10278 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/960/06960492.pdf [firstpage_image] =>[orig_patent_app_number] => 10401870 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/401870
Semiconductor device having multilayer wiring and manufacturing method therefor Mar 30, 2003 Issued
Array ( [id] => 1031045 [patent_doc_number] => 06878597 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-12 [patent_title] => 'Methods of forming source/drain regions using multilayer side wall spacers and structures so formed' [patent_app_type] => utility [patent_app_number] => 10/397970 [patent_app_country] => US [patent_app_date] => 2003-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 3597 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/878/06878597.pdf [firstpage_image] =>[orig_patent_app_number] => 10397970 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/397970
Methods of forming source/drain regions using multilayer side wall spacers and structures so formed Mar 25, 2003 Issued
Array ( [id] => 6827628 [patent_doc_number] => 20030178686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-25 [patent_title] => 'Stacked capacitor-type semiconductor storage device and manufacturing method thereof' [patent_app_type] => new [patent_app_number] => 10/388462 [patent_app_country] => US [patent_app_date] => 2003-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5306 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20030178686.pdf [firstpage_image] =>[orig_patent_app_number] => 10388462 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/388462
Stacked capacitor-type semiconductor storage device and manufacturing method thereof Mar 16, 2003 Issued
Array ( [id] => 7673223 [patent_doc_number] => 20040180556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-16 [patent_title] => 'Method for modifying dielectric characteristics of dielectric layers' [patent_app_type] => new [patent_app_number] => 10/387160 [patent_app_country] => US [patent_app_date] => 2003-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5216 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20040180556.pdf [firstpage_image] =>[orig_patent_app_number] => 10387160 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/387160
Method for modifying dielectric characteristics of dielectric layers Mar 10, 2003 Issued
Array ( [id] => 6730369 [patent_doc_number] => 20030186559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-02 [patent_title] => 'Method of manufacturing a compound semiconductor by heating a layered structure including rare earth transition metal' [patent_app_type] => new [patent_app_number] => 10/382070 [patent_app_country] => US [patent_app_date] => 2003-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3885 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20030186559.pdf [firstpage_image] =>[orig_patent_app_number] => 10382070 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/382070
Method of manufacturing a compound semiconductor by heating a layered structure including rare earth transition metal Mar 3, 2003 Issued
Array ( [id] => 1073673 [patent_doc_number] => 06838338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-04 [patent_title] => 'Integrated capacitor bottom electrode for use with conformal dielectric' [patent_app_type] => utility [patent_app_number] => 10/378019 [patent_app_country] => US [patent_app_date] => 2003-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4303 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/838/06838338.pdf [firstpage_image] =>[orig_patent_app_number] => 10378019 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/378019
Integrated capacitor bottom electrode for use with conformal dielectric Feb 26, 2003 Issued
Array ( [id] => 7221743 [patent_doc_number] => 20040072392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-15 [patent_title] => 'METHOD OF FORMING A LOW TEMPERATURE POLYSILICON THIN FILM TRANSISTOR' [patent_app_type] => new [patent_app_number] => 10/248770 [patent_app_country] => US [patent_app_date] => 2003-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4444 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20040072392.pdf [firstpage_image] =>[orig_patent_app_number] => 10248770 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/248770
Method of forming a low temperature polysilicon thin film transistor Feb 15, 2003 Issued
Array ( [id] => 6912451 [patent_doc_number] => 20050176209 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-11 [patent_title] => 'Embedded passive components' [patent_app_type] => utility [patent_app_number] => 10/366924 [patent_app_country] => US [patent_app_date] => 2003-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2370 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20050176209.pdf [firstpage_image] =>[orig_patent_app_number] => 10366924 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/366924
Embedded passive components Feb 13, 2003 Abandoned
Array ( [id] => 1012690 [patent_doc_number] => 06897161 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-24 [patent_title] => 'Method of cleaning component in plasma processing chamber and method of producing semiconductor devices' [patent_app_type] => utility [patent_app_number] => 10/361570 [patent_app_country] => US [patent_app_date] => 2003-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 9585 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/897/06897161.pdf [firstpage_image] =>[orig_patent_app_number] => 10361570 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/361570
Method of cleaning component in plasma processing chamber and method of producing semiconductor devices Feb 10, 2003 Issued
Array ( [id] => 6912433 [patent_doc_number] => 20050176191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-11 [patent_title] => 'Method for fabricating a notched gate structure of a field effect transistor' [patent_app_type] => utility [patent_app_number] => 10/358970 [patent_app_country] => US [patent_app_date] => 2003-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4398 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20050176191.pdf [firstpage_image] =>[orig_patent_app_number] => 10358970 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/358970
Method for fabricating a notched gate structure of a field effect transistor Feb 3, 2003 Abandoned
Array ( [id] => 1068690 [patent_doc_number] => 06844216 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-18 [patent_title] => 'Method of attaching solder balls to BGA package utilizing a tool to pick and dip the solder ball in flux' [patent_app_type] => utility [patent_app_number] => 10/358630 [patent_app_country] => US [patent_app_date] => 2003-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 4288 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/844/06844216.pdf [firstpage_image] =>[orig_patent_app_number] => 10358630 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/358630
Method of attaching solder balls to BGA package utilizing a tool to pick and dip the solder ball in flux Feb 3, 2003 Issued
Array ( [id] => 7452920 [patent_doc_number] => 20040118676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-24 [patent_title] => 'Plating apparatus and plating method' [patent_app_type] => new [patent_app_number] => 10/347770 [patent_app_country] => US [patent_app_date] => 2003-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 56509 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0118/20040118676.pdf [firstpage_image] =>[orig_patent_app_number] => 10347770 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/347770
Plating apparatus and plating method Jan 16, 2003 Issued
Array ( [id] => 627021 [patent_doc_number] => 07135404 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-14 [patent_title] => 'Method for applying metal features onto barrier layers using electrochemical deposition' [patent_app_type] => utility [patent_app_number] => 10/470287 [patent_app_country] => US [patent_app_date] => 2003-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 21 [patent_no_of_words] => 8466 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/135/07135404.pdf [firstpage_image] =>[orig_patent_app_number] => 10470287 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/470287
Method for applying metal features onto barrier layers using electrochemical deposition Jan 9, 2003 Issued
Array ( [id] => 1149686 [patent_doc_number] => 06770571 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-03 [patent_title] => 'Barrier in gate stack for improved gate dielectric integrity' [patent_app_type] => B2 [patent_app_number] => 10/339731 [patent_app_country] => US [patent_app_date] => 2003-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3636 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/770/06770571.pdf [firstpage_image] =>[orig_patent_app_number] => 10339731 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/339731
Barrier in gate stack for improved gate dielectric integrity Jan 7, 2003 Issued
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