
Lalrinfamkim Hmar Malsawma
Examiner (ID: 2370)
| Most Active Art Unit | 2892 |
| Art Unit(s) | 2823, 2892, 2825 |
| Total Applications | 1951 |
| Issued Applications | 1709 |
| Pending Applications | 105 |
| Abandoned Applications | 179 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7629874
[patent_doc_number] => 06818482
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-11-16
[patent_title] => 'Method for trench isolation for thyristor-based device'
[patent_app_type] => B1
[patent_app_number] => 10/263370
[patent_app_country] => US
[patent_app_date] => 2002-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 13
[patent_no_of_words] => 5780
[patent_no_of_claims] => 48
[patent_no_of_ind_claims] => 20
[patent_words_short_claim] => 19
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/818/06818482.pdf
[firstpage_image] =>[orig_patent_app_number] => 10263370
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/263370 | Method for trench isolation for thyristor-based device | Sep 30, 2002 | Issued |
Array
(
[id] => 1144928
[patent_doc_number] => 06777800
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-08-17
[patent_title] => 'Semiconductor die package including drain clip'
[patent_app_type] => B2
[patent_app_number] => 10/262170
[patent_app_country] => US
[patent_app_date] => 2002-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3726
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/777/06777800.pdf
[firstpage_image] =>[orig_patent_app_number] => 10262170
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/262170 | Semiconductor die package including drain clip | Sep 29, 2002 | Issued |
Array
(
[id] => 969020
[patent_doc_number] => 06940298
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-09-06
[patent_title] => 'High fidelity electrical probe'
[patent_app_type] => utility
[patent_app_number] => 10/262370
[patent_app_country] => US
[patent_app_date] => 2002-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1674
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/940/06940298.pdf
[firstpage_image] =>[orig_patent_app_number] => 10262370
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/262370 | High fidelity electrical probe | Sep 29, 2002 | Issued |
Array
(
[id] => 6801284
[patent_doc_number] => 20030096449
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-05-22
[patent_title] => 'Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument'
[patent_app_type] => new
[patent_app_number] => 10/254600
[patent_app_country] => US
[patent_app_date] => 2002-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 12065
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0096/20030096449.pdf
[firstpage_image] =>[orig_patent_app_number] => 10254600
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/254600 | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument | Sep 25, 2002 | Issued |
Array
(
[id] => 1126383
[patent_doc_number] => 06790688
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-09-14
[patent_title] => 'Method of high pass filtering a data set'
[patent_app_type] => B2
[patent_app_number] => 10/252416
[patent_app_country] => US
[patent_app_date] => 2002-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 2808
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/790/06790688.pdf
[firstpage_image] =>[orig_patent_app_number] => 10252416
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/252416 | Method of high pass filtering a data set | Sep 23, 2002 | Issued |
Array
(
[id] => 7625553
[patent_doc_number] => 06723616
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-04-20
[patent_title] => 'Process of increasing screen dielectric thickness'
[patent_app_type] => B2
[patent_app_number] => 10/253870
[patent_app_country] => US
[patent_app_date] => 2002-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 7
[patent_no_of_words] => 2824
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 13
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/723/06723616.pdf
[firstpage_image] =>[orig_patent_app_number] => 10253870
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/253870 | Process of increasing screen dielectric thickness | Sep 23, 2002 | Issued |
Array
(
[id] => 6683471
[patent_doc_number] => 20030119335
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-06-26
[patent_title] => 'Process for producing nanoporous dielectric films at high pH'
[patent_app_type] => new
[patent_app_number] => 10/246642
[patent_app_country] => US
[patent_app_date] => 2002-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 5765
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0119/20030119335.pdf
[firstpage_image] =>[orig_patent_app_number] => 10246642
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/246642 | Process for producing nanoporous dielectric films at high pH | Sep 17, 2002 | Abandoned |
Array
(
[id] => 7474432
[patent_doc_number] => 20040054980
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-03-18
[patent_title] => 'Embossed mask lithography'
[patent_app_type] => new
[patent_app_number] => 10/244862
[patent_app_country] => US
[patent_app_date] => 2002-09-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3859
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0054/20040054980.pdf
[firstpage_image] =>[orig_patent_app_number] => 10244862
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/244862 | Embossed mask lithography | Sep 16, 2002 | Issued |
Array
(
[id] => 6778839
[patent_doc_number] => 20030049920
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-03-13
[patent_title] => 'Manufacturing method of semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/237770
[patent_app_country] => US
[patent_app_date] => 2002-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4502
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0049/20030049920.pdf
[firstpage_image] =>[orig_patent_app_number] => 10237770
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/237770 | Manufacturing method of semiconductor device | Sep 8, 2002 | Abandoned |
Array
(
[id] => 1065609
[patent_doc_number] => 06846735
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-01-25
[patent_title] => 'Compliant test probe with jagged contact surface'
[patent_app_type] => utility
[patent_app_number] => 10/235270
[patent_app_country] => US
[patent_app_date] => 2002-09-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 75
[patent_figures_cnt] => 223
[patent_no_of_words] => 11975
[patent_no_of_claims] => 155
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 30
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/846/06846735.pdf
[firstpage_image] =>[orig_patent_app_number] => 10235270
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/235270 | Compliant test probe with jagged contact surface | Sep 4, 2002 | Issued |
Array
(
[id] => 7135247
[patent_doc_number] => 20040043634
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-03-04
[patent_title] => 'Systems and methods for forming metal-doped alumina'
[patent_app_type] => new
[patent_app_number] => 10/229780
[patent_app_country] => US
[patent_app_date] => 2002-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 8469
[patent_no_of_claims] => 57
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 16
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0043/20040043634.pdf
[firstpage_image] =>[orig_patent_app_number] => 10229780
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/229780 | Systems and methods for forming metal-doped alumina | Aug 27, 2002 | Issued |
Array
(
[id] => 1145989
[patent_doc_number] => 06773945
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-08-10
[patent_title] => 'Method of manufacturing a waveguide optical semiconductor device'
[patent_app_type] => B2
[patent_app_number] => 10/212170
[patent_app_country] => US
[patent_app_date] => 2002-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 36
[patent_no_of_words] => 4494
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/773/06773945.pdf
[firstpage_image] =>[orig_patent_app_number] => 10212170
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/212170 | Method of manufacturing a waveguide optical semiconductor device | Aug 5, 2002 | Issued |
Array
(
[id] => 6530378
[patent_doc_number] => 20020192909
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-12-19
[patent_title] => 'Nucleation for improved flash erase characteristics'
[patent_app_type] => new
[patent_app_number] => 10/212937
[patent_app_country] => US
[patent_app_date] => 2002-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4643
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0192/20020192909.pdf
[firstpage_image] =>[orig_patent_app_number] => 10212937
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/212937 | Nucleation for improved flash erase characteristics | Aug 4, 2002 | Issued |
Array
(
[id] => 6716084
[patent_doc_number] => 20030027432
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-02-06
[patent_title] => 'Method for manufacturing laminated dielectrics'
[patent_app_type] => new
[patent_app_number] => 10/209670
[patent_app_country] => US
[patent_app_date] => 2002-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 7623
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0027/20030027432.pdf
[firstpage_image] =>[orig_patent_app_number] => 10209670
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/209670 | Method for manufacturing laminated dielectrics | Jul 31, 2002 | Issued |
Array
(
[id] => 6745234
[patent_doc_number] => 20030022417
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-01-30
[patent_title] => 'Micro eletro-mechanical component and system architecture'
[patent_app_type] => new
[patent_app_number] => 10/182422
[patent_app_country] => US
[patent_app_date] => 2002-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4413
[patent_no_of_claims] => 41
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0022/20030022417.pdf
[firstpage_image] =>[orig_patent_app_number] => 10182422
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/182422 | Micro eletro-mechanical component and system architecture | Jul 28, 2002 | Issued |
Array
(
[id] => 7612855
[patent_doc_number] => 06902979
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-06-07
[patent_title] => 'Method for manufacturing mask ROM'
[patent_app_type] => utility
[patent_app_number] => 10/201860
[patent_app_country] => US
[patent_app_date] => 2002-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 18
[patent_no_of_words] => 3756
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 195
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/902/06902979.pdf
[firstpage_image] =>[orig_patent_app_number] => 10201860
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/201860 | Method for manufacturing mask ROM | Jul 23, 2002 | Issued |
Array
(
[id] => 6851612
[patent_doc_number] => 20030143815
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-07-31
[patent_title] => 'Semiconductor device and method of fabricating the same'
[patent_app_type] => new
[patent_app_number] => 10/197870
[patent_app_country] => US
[patent_app_date] => 2002-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 4505
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0143/20030143815.pdf
[firstpage_image] =>[orig_patent_app_number] => 10197870
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/197870 | Semiconductor device and method of fabricating the same | Jul 18, 2002 | Issued |
Array
(
[id] => 6745243
[patent_doc_number] => 20030022426
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-01-30
[patent_title] => 'Manufacturing method of semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/197670
[patent_app_country] => US
[patent_app_date] => 2002-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 8993
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0022/20030022426.pdf
[firstpage_image] =>[orig_patent_app_number] => 10197670
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/197670 | Manufacturing method of semiconductor device | Jul 17, 2002 | Issued |
Array
(
[id] => 6720920
[patent_doc_number] => 20030054609
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-03-20
[patent_title] => 'Methods of writing/erasing of nonvolatile semiconductor storage device'
[patent_app_type] => new
[patent_app_number] => 10/196170
[patent_app_country] => US
[patent_app_date] => 2002-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6966
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 316
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0054/20030054609.pdf
[firstpage_image] =>[orig_patent_app_number] => 10196170
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/196170 | Methods of writing/erasing of nonvolatile semiconductor storage device | Jul 16, 2002 | Issued |
Array
(
[id] => 1335960
[patent_doc_number] => 06593176
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-07-15
[patent_title] => 'METHOD FOR FORMING PHASE-CHANGE MEMORY BIPOLAR ARRAY UTILIZING A SINGLE SHALLOW TRENCH ISOLATION FOR CREATING AN INDIVIDUAL ACTIVE AREA REGION FOR TWO MEMORY ARRAY ELEMENTS AND ONE BIPOLAR BASE CONTACT'
[patent_app_type] => B2
[patent_app_number] => 10/196870
[patent_app_country] => US
[patent_app_date] => 2002-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 22
[patent_no_of_words] => 8298
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/593/06593176.pdf
[firstpage_image] =>[orig_patent_app_number] => 10196870
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/196870 | METHOD FOR FORMING PHASE-CHANGE MEMORY BIPOLAR ARRAY UTILIZING A SINGLE SHALLOW TRENCH ISOLATION FOR CREATING AN INDIVIDUAL ACTIVE AREA REGION FOR TWO MEMORY ARRAY ELEMENTS AND ONE BIPOLAR BASE CONTACT | Jul 14, 2002 | Issued |