
Lalrinfamkim Hmar Malsawma
Examiner (ID: 5479)
| Most Active Art Unit | 2892 |
| Art Unit(s) | 2825, 2892, 2823 |
| Total Applications | 2001 |
| Issued Applications | 1735 |
| Pending Applications | 112 |
| Abandoned Applications | 179 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6851612
[patent_doc_number] => 20030143815
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-07-31
[patent_title] => 'Semiconductor device and method of fabricating the same'
[patent_app_type] => new
[patent_app_number] => 10/197870
[patent_app_country] => US
[patent_app_date] => 2002-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 4505
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0143/20030143815.pdf
[firstpage_image] =>[orig_patent_app_number] => 10197870
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/197870 | Semiconductor device and method of fabricating the same | Jul 18, 2002 | Issued |
Array
(
[id] => 6745243
[patent_doc_number] => 20030022426
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-01-30
[patent_title] => 'Manufacturing method of semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/197670
[patent_app_country] => US
[patent_app_date] => 2002-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 8993
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0022/20030022426.pdf
[firstpage_image] =>[orig_patent_app_number] => 10197670
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/197670 | Manufacturing method of semiconductor device | Jul 17, 2002 | Issued |
Array
(
[id] => 6720920
[patent_doc_number] => 20030054609
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-03-20
[patent_title] => 'Methods of writing/erasing of nonvolatile semiconductor storage device'
[patent_app_type] => new
[patent_app_number] => 10/196170
[patent_app_country] => US
[patent_app_date] => 2002-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6966
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 316
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0054/20030054609.pdf
[firstpage_image] =>[orig_patent_app_number] => 10196170
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/196170 | Methods of writing/erasing of nonvolatile semiconductor storage device | Jul 16, 2002 | Issued |
Array
(
[id] => 1192890
[patent_doc_number] => 06730534
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-05-04
[patent_title] => 'Method of manufacturing three-dimensional structure and method of manufacturing oscillator'
[patent_app_type] => B2
[patent_app_number] => 10/195870
[patent_app_country] => US
[patent_app_date] => 2002-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 23
[patent_no_of_words] => 4868
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/730/06730534.pdf
[firstpage_image] =>[orig_patent_app_number] => 10195870
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/195870 | Method of manufacturing three-dimensional structure and method of manufacturing oscillator | Jul 14, 2002 | Issued |
Array
(
[id] => 1335960
[patent_doc_number] => 06593176
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-07-15
[patent_title] => 'METHOD FOR FORMING PHASE-CHANGE MEMORY BIPOLAR ARRAY UTILIZING A SINGLE SHALLOW TRENCH ISOLATION FOR CREATING AN INDIVIDUAL ACTIVE AREA REGION FOR TWO MEMORY ARRAY ELEMENTS AND ONE BIPOLAR BASE CONTACT'
[patent_app_type] => B2
[patent_app_number] => 10/196870
[patent_app_country] => US
[patent_app_date] => 2002-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 22
[patent_no_of_words] => 8298
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/593/06593176.pdf
[firstpage_image] =>[orig_patent_app_number] => 10196870
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/196870 | METHOD FOR FORMING PHASE-CHANGE MEMORY BIPOLAR ARRAY UTILIZING A SINGLE SHALLOW TRENCH ISOLATION FOR CREATING AN INDIVIDUAL ACTIVE AREA REGION FOR TWO MEMORY ARRAY ELEMENTS AND ONE BIPOLAR BASE CONTACT | Jul 14, 2002 | Issued |
Array
(
[id] => 6735646
[patent_doc_number] => 20030013281
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-01-16
[patent_title] => 'Polysilicon crystallizing method, method of fabricating thin film transistor using the same, and method of fabricating liquid crystal display thereof'
[patent_app_type] => new
[patent_app_number] => 10/189770
[patent_app_country] => US
[patent_app_date] => 2002-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4097
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 42
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0013/20030013281.pdf
[firstpage_image] =>[orig_patent_app_number] => 10189770
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/189770 | Polysilicon crystallizing method, method of fabricating thin film transistor using the same, and method of fabricating liquid crystal display thereof | Jul 7, 2002 | Issued |
Array
(
[id] => 6825308
[patent_doc_number] => 20030235930
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-12-25
[patent_title] => 'Multi-impression nanofeature production'
[patent_app_type] => new
[patent_app_number] => 10/179570
[patent_app_country] => US
[patent_app_date] => 2002-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 3550
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 41
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0235/20030235930.pdf
[firstpage_image] =>[orig_patent_app_number] => 10179570
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/179570 | Multi-impression nanofeature production | Jun 24, 2002 | Abandoned |
Array
(
[id] => 1212720
[patent_doc_number] => 06709930
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-03-23
[patent_title] => 'Thicker oxide formation at the trench bottom by selective oxide deposition'
[patent_app_type] => B2
[patent_app_number] => 10/176570
[patent_app_country] => US
[patent_app_date] => 2002-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 2636
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/709/06709930.pdf
[firstpage_image] =>[orig_patent_app_number] => 10176570
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/176570 | Thicker oxide formation at the trench bottom by selective oxide deposition | Jun 20, 2002 | Issued |
Array
(
[id] => 996499
[patent_doc_number] => 06913938
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-07-05
[patent_title] => 'Feedback control of plasma-enhanced chemical vapor deposition processes'
[patent_app_type] => utility
[patent_app_number] => 10/174370
[patent_app_country] => US
[patent_app_date] => 2002-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 9668
[patent_no_of_claims] => 81
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/913/06913938.pdf
[firstpage_image] =>[orig_patent_app_number] => 10174370
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/174370 | Feedback control of plasma-enhanced chemical vapor deposition processes | Jun 17, 2002 | Issued |
Array
(
[id] => 6327278
[patent_doc_number] => 20020197793
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-12-26
[patent_title] => 'Low thermal budget metal oxide deposition for capacitor structures'
[patent_app_type] => new
[patent_app_number] => 09/936070
[patent_app_country] => US
[patent_app_date] => 2002-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 10124
[patent_no_of_claims] => 64
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 33
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0197/20020197793.pdf
[firstpage_image] =>[orig_patent_app_number] => 09936070
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/936070 | Low thermal budget metal oxide deposition for capacitor structures | Jun 5, 2002 | Abandoned |
| 10/070370 | A semiconductor device and method of manufacturing the same | Jun 3, 2002 | Abandoned |
Array
(
[id] => 1080491
[patent_doc_number] => 06835649
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-12-28
[patent_title] => 'Tungsten plug with conductor capping layer'
[patent_app_type] => B2
[patent_app_number] => 10/161570
[patent_app_country] => US
[patent_app_date] => 2002-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 3527
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/835/06835649.pdf
[firstpage_image] =>[orig_patent_app_number] => 10161570
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/161570 | Tungsten plug with conductor capping layer | Jun 2, 2002 | Issued |
Array
(
[id] => 1225074
[patent_doc_number] => 06700144
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-03-02
[patent_title] => 'Semiconductor device and method for manufacturing the same'
[patent_app_type] => B2
[patent_app_number] => 10/155470
[patent_app_country] => US
[patent_app_date] => 2002-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 23
[patent_no_of_words] => 5993
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/700/06700144.pdf
[firstpage_image] =>[orig_patent_app_number] => 10155470
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/155470 | Semiconductor device and method for manufacturing the same | May 23, 2002 | Issued |
Array
(
[id] => 1239564
[patent_doc_number] => 06686222
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-02-03
[patent_title] => 'Stacked semiconductor device manufacturing method'
[patent_app_type] => B2
[patent_app_number] => 10/147070
[patent_app_country] => US
[patent_app_date] => 2002-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 19
[patent_no_of_words] => 5134
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/686/06686222.pdf
[firstpage_image] =>[orig_patent_app_number] => 10147070
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/147070 | Stacked semiconductor device manufacturing method | May 16, 2002 | Issued |
Array
(
[id] => 6770073
[patent_doc_number] => 20030216013
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-11-20
[patent_title] => 'Method of controlling grain size in a polysilicon layer and in semiconductor devices having polysilicone structures'
[patent_app_type] => new
[patent_app_number] => 10/147270
[patent_app_country] => US
[patent_app_date] => 2002-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 6305
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 24
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0216/20030216013.pdf
[firstpage_image] =>[orig_patent_app_number] => 10147270
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/147270 | Method of controlling grain size in a polysilicon layer and in semiconductor devices having polysilicon structures | May 14, 2002 | Issued |
Array
(
[id] => 1175891
[patent_doc_number] => 06750507
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-06-15
[patent_title] => 'Super-self-aligned trench-gated DMOS with reduced on-resistance'
[patent_app_type] => B2
[patent_app_number] => 10/146668
[patent_app_country] => US
[patent_app_date] => 2002-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 58
[patent_figures_cnt] => 90
[patent_no_of_words] => 16719
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/750/06750507.pdf
[firstpage_image] =>[orig_patent_app_number] => 10146668
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/146668 | Super-self-aligned trench-gated DMOS with reduced on-resistance | May 13, 2002 | Issued |
Array
(
[id] => 6048160
[patent_doc_number] => 20020168821
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-11-14
[patent_title] => 'Fabrication process for a super-self-aligned trench-gated DMOS with reduced on-resistance'
[patent_app_type] => new
[patent_app_number] => 10/146568
[patent_app_country] => US
[patent_app_date] => 2002-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 59
[patent_figures_cnt] => 59
[patent_no_of_words] => 16960
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0168/20020168821.pdf
[firstpage_image] =>[orig_patent_app_number] => 10146568
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/146568 | Fabrication process for a super-self-aligned trench-gated DMOS with reduced on-resistance | May 13, 2002 | Issued |
Array
(
[id] => 6636067
[patent_doc_number] => 20030211682
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-11-13
[patent_title] => 'Method for fabricating a gate electrode'
[patent_app_type] => new
[patent_app_number] => 10/141870
[patent_app_country] => US
[patent_app_date] => 2002-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2009
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0211/20030211682.pdf
[firstpage_image] =>[orig_patent_app_number] => 10141870
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/141870 | Method for fabricating a gate electrode | May 9, 2002 | Abandoned |
Array
(
[id] => 1239770
[patent_doc_number] => 06686293
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-02-03
[patent_title] => 'Method of etching a trench in a silicon-containing dielectric material'
[patent_app_type] => B2
[patent_app_number] => 10/144570
[patent_app_country] => US
[patent_app_date] => 2002-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 32
[patent_no_of_words] => 8005
[patent_no_of_claims] => 46
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/686/06686293.pdf
[firstpage_image] =>[orig_patent_app_number] => 10144570
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/144570 | Method of etching a trench in a silicon-containing dielectric material | May 9, 2002 | Issued |
Array
(
[id] => 7629823
[patent_doc_number] => 06818533
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-11-16
[patent_title] => 'Epitaxial plasma enhanced chemical vapor deposition (PECVD) method providing epitaxial layer with attenuated defects'
[patent_app_type] => B2
[patent_app_number] => 10/143470
[patent_app_country] => US
[patent_app_date] => 2002-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 3323
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 10
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/818/06818533.pdf
[firstpage_image] =>[orig_patent_app_number] => 10143470
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/143470 | Epitaxial plasma enhanced chemical vapor deposition (PECVD) method providing epitaxial layer with attenuated defects | May 8, 2002 | Issued |