Search

Lalrinfamkim Hmar Malsawma

Examiner (ID: 2370)

Most Active Art Unit
2892
Art Unit(s)
2823, 2892, 2825
Total Applications
1951
Issued Applications
1709
Pending Applications
105
Abandoned Applications
179

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6716079 [patent_doc_number] => 20030027427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-06 [patent_title] => 'Integrated system for oxide etching and metal liner deposition' [patent_app_type] => new [patent_app_number] => 09/922980 [patent_app_country] => US [patent_app_date] => 2001-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6734 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20030027427.pdf [firstpage_image] =>[orig_patent_app_number] => 09922980 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/922980
Integrated system for oxide etching and metal liner deposition Aug 5, 2001 Abandoned
Array ( [id] => 1040600 [patent_doc_number] => 06869898 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-22 [patent_title] => 'Quartz glass jig for processing apparatus using plasma' [patent_app_type] => utility [patent_app_number] => 10/343470 [patent_app_country] => US [patent_app_date] => 2001-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2499 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/869/06869898.pdf [firstpage_image] =>[orig_patent_app_number] => 10343470 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/343470
Quartz glass jig for processing apparatus using plasma Jul 29, 2001 Issued
Array ( [id] => 6141732 [patent_doc_number] => 20020001886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-03 [patent_title] => 'Method of manufacturing thin film transistor' [patent_app_type] => new [patent_app_number] => 09/916913 [patent_app_country] => US [patent_app_date] => 2001-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11875 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20020001886.pdf [firstpage_image] =>[orig_patent_app_number] => 09916913 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/916913
Thin film transistor formed on a resin substrate Jul 26, 2001 Issued
Array ( [id] => 720002 [patent_doc_number] => 07049233 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-23 [patent_title] => 'Apparatus and method for manufacturing thin film electrode of hydrous ruthenium oxide' [patent_app_type] => utility [patent_app_number] => 10/398761 [patent_app_country] => US [patent_app_date] => 2001-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2945 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/049/07049233.pdf [firstpage_image] =>[orig_patent_app_number] => 10398761 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/398761
Apparatus and method for manufacturing thin film electrode of hydrous ruthenium oxide Jul 25, 2001 Issued
Array ( [id] => 1375921 [patent_doc_number] => 06559025 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-06 [patent_title] => 'Method for manufacturing a capacitor' [patent_app_type] => B2 [patent_app_number] => 09/909510 [patent_app_country] => US [patent_app_date] => 2001-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2347 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/559/06559025.pdf [firstpage_image] =>[orig_patent_app_number] => 09909510 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/909510
Method for manufacturing a capacitor Jul 19, 2001 Issued
Array ( [id] => 1066274 [patent_doc_number] => 06847097 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-25 [patent_title] => 'Glass substrate assembly, semiconductor device and method of heat-treating glass substrate' [patent_app_type] => utility [patent_app_number] => 09/904906 [patent_app_country] => US [patent_app_date] => 2001-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 8139 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/847/06847097.pdf [firstpage_image] =>[orig_patent_app_number] => 09904906 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/904906
Glass substrate assembly, semiconductor device and method of heat-treating glass substrate Jul 15, 2001 Issued
Array ( [id] => 1146746 [patent_doc_number] => 06774047 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-10 [patent_title] => 'Method of manufacturing a semiconductor integrated circuit device' [patent_app_type] => B2 [patent_app_number] => 09/902673 [patent_app_country] => US [patent_app_date] => 2001-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 5686 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/774/06774047.pdf [firstpage_image] =>[orig_patent_app_number] => 09902673 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/902673
Method of manufacturing a semiconductor integrated circuit device Jul 11, 2001 Issued
Array ( [id] => 1123504 [patent_doc_number] => 06794305 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-21 [patent_title] => 'Method of manufacturing a semiconductor integrated circuit device' [patent_app_type] => B2 [patent_app_number] => 09/902672 [patent_app_country] => US [patent_app_date] => 2001-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 5682 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/794/06794305.pdf [firstpage_image] =>[orig_patent_app_number] => 09902672 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/902672
Method of manufacturing a semiconductor integrated circuit device Jul 11, 2001 Issued
Array ( [id] => 6725158 [patent_doc_number] => 20030207470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-06 [patent_title] => 'METAL INSULATOR SEMICONDUCTOR STRUCTURE WITH POLARIZATION-COMPATIBLE BUFFER LAYER' [patent_app_type] => new [patent_app_number] => 09/899670 [patent_app_country] => US [patent_app_date] => 2001-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9196 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20030207470.pdf [firstpage_image] =>[orig_patent_app_number] => 09899670 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/899670
Metal insulator structure with polarization-compatible buffer layer Jul 4, 2001 Issued
Array ( [id] => 6898577 [patent_doc_number] => 20010046742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-29 [patent_title] => 'Barrier in gate stack for improved gate dielectric integrity' [patent_app_type] => new [patent_app_number] => 09/894070 [patent_app_country] => US [patent_app_date] => 2001-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3644 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20010046742.pdf [firstpage_image] =>[orig_patent_app_number] => 09894070 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/894070
Barrier in gate stack for improved gate dielectric integrity Jun 27, 2001 Issued
Array ( [id] => 6755863 [patent_doc_number] => 20030003640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Advanced contact integration scheme for deep-sub-150 NM devices' [patent_app_type] => new [patent_app_number] => 09/892620 [patent_app_country] => US [patent_app_date] => 2001-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2120 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20030003640.pdf [firstpage_image] =>[orig_patent_app_number] => 09892620 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/892620
Advanced contact integration scheme for deep-sub-150 nm devices Jun 27, 2001 Issued
Array ( [id] => 1149842 [patent_doc_number] => 06774413 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-10 [patent_title] => 'Integrated circuit structure with programmable connector/isolator' [patent_app_type] => B2 [patent_app_number] => 09/882900 [patent_app_country] => US [patent_app_date] => 2001-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2528 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/774/06774413.pdf [firstpage_image] =>[orig_patent_app_number] => 09882900 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/882900
Integrated circuit structure with programmable connector/isolator Jun 14, 2001 Issued
Array ( [id] => 1390160 [patent_doc_number] => 06544856 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-08 [patent_title] => 'Method for increasing the trench capacitance' [patent_app_type] => B2 [patent_app_number] => 09/880180 [patent_app_country] => US [patent_app_date] => 2001-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2303 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/544/06544856.pdf [firstpage_image] =>[orig_patent_app_number] => 09880180 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/880180
Method for increasing the trench capacitance Jun 12, 2001 Issued
Array ( [id] => 1316096 [patent_doc_number] => 06611032 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-26 [patent_title] => 'Methods for forming wordlines, transistor gates, and conductive interconnects, and wordline, transistor gate, and conductive interconnect structures' [patent_app_type] => B2 [patent_app_number] => 09/879742 [patent_app_country] => US [patent_app_date] => 2001-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 5519 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/611/06611032.pdf [firstpage_image] =>[orig_patent_app_number] => 09879742 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/879742
Methods for forming wordlines, transistor gates, and conductive interconnects, and wordline, transistor gate, and conductive interconnect structures Jun 10, 2001 Issued
Array ( [id] => 1324223 [patent_doc_number] => 06602765 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-05 [patent_title] => 'Fabrication method of thin-film semiconductor device' [patent_app_type] => B2 [patent_app_number] => 09/875910 [patent_app_country] => US [patent_app_date] => 2001-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 16253 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/602/06602765.pdf [firstpage_image] =>[orig_patent_app_number] => 09875910 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/875910
Fabrication method of thin-film semiconductor device Jun 7, 2001 Issued
Array ( [id] => 6921585 [patent_doc_number] => 20010029070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-11 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => new [patent_app_number] => 09/874670 [patent_app_country] => US [patent_app_date] => 2001-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 18476 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20010029070.pdf [firstpage_image] =>[orig_patent_app_number] => 09874670 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/874670
Semiconductor device and manufacturing method thereof Jun 4, 2001 Issued
Array ( [id] => 1202626 [patent_doc_number] => 06720200 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-13 [patent_title] => 'Field effect transistor and fabrication process thereof' [patent_app_type] => B2 [patent_app_number] => 09/862870 [patent_app_country] => US [patent_app_date] => 2001-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 45 [patent_no_of_words] => 8623 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/720/06720200.pdf [firstpage_image] =>[orig_patent_app_number] => 09862870 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/862870
Field effect transistor and fabrication process thereof May 21, 2001 Issued
Array ( [id] => 1449995 [patent_doc_number] => 06455390 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-09-24 [patent_title] => 'Method of manufacturing hetero-junction bipolar transistor' [patent_app_type] => B2 [patent_app_number] => 09/861614 [patent_app_country] => US [patent_app_date] => 2001-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 6266 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/455/06455390.pdf [firstpage_image] =>[orig_patent_app_number] => 09861614 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/861614
Method of manufacturing hetero-junction bipolar transistor May 21, 2001 Issued
Array ( [id] => 1440084 [patent_doc_number] => 06495440 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-17 [patent_title] => 'Method to prevent an ITO from opening' [patent_app_type] => B2 [patent_app_number] => 09/846300 [patent_app_country] => US [patent_app_date] => 2001-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1670 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/495/06495440.pdf [firstpage_image] =>[orig_patent_app_number] => 09846300 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/846300
Method to prevent an ITO from opening May 1, 2001 Issued
Array ( [id] => 6176769 [patent_doc_number] => 20020155686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-24 [patent_title] => 'Fabrication method for suppressing a hot carrier effect and leakage currents of I/O devices' [patent_app_type] => new [patent_app_number] => 09/840710 [patent_app_country] => US [patent_app_date] => 2001-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2260 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20020155686.pdf [firstpage_image] =>[orig_patent_app_number] => 09840710 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/840710
Fabrication method for suppressing a hot carrier effect and leakage currents of I/O devices Apr 23, 2001 Abandoned
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