Search

Lalrinfamkim Hmar Malsawma

Examiner (ID: 2370)

Most Active Art Unit
2892
Art Unit(s)
2823, 2892, 2825
Total Applications
1951
Issued Applications
1709
Pending Applications
105
Abandoned Applications
179

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1486773 [patent_doc_number] => 06365954 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Metal-polycrystalline silicon-n-well multiple layered capacitor' [patent_app_type] => B1 [patent_app_number] => 09/679513 [patent_app_country] => US [patent_app_date] => 2000-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3842 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/365/06365954.pdf [firstpage_image] =>[orig_patent_app_number] => 09679513 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/679513
Metal-polycrystalline silicon-n-well multiple layered capacitor Oct 5, 2000 Issued
Array ( [id] => 1478191 [patent_doc_number] => 06451693 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Double silicide formation in polysicon gate without silicide in source/drain extensions' [patent_app_type] => B1 [patent_app_number] => 09/679370 [patent_app_country] => US [patent_app_date] => 2000-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 22 [patent_no_of_words] => 3967 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/451/06451693.pdf [firstpage_image] =>[orig_patent_app_number] => 09679370 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/679370
Double silicide formation in polysicon gate without silicide in source/drain extensions Oct 4, 2000 Issued
Array ( [id] => 1418260 [patent_doc_number] => 06514835 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Stress control of thin films by mechanical deformation of wafer substrate' [patent_app_type] => B1 [patent_app_number] => 09/676283 [patent_app_country] => US [patent_app_date] => 2000-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 18 [patent_no_of_words] => 5988 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/514/06514835.pdf [firstpage_image] =>[orig_patent_app_number] => 09676283 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/676283
Stress control of thin films by mechanical deformation of wafer substrate Sep 27, 2000 Issued
Array ( [id] => 1336585 [patent_doc_number] => 06597037 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-22 [patent_title] => 'Programmable memory address decode array with vertical transistors' [patent_app_type] => B1 [patent_app_number] => 09/669281 [patent_app_country] => US [patent_app_date] => 2000-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 9853 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/597/06597037.pdf [firstpage_image] =>[orig_patent_app_number] => 09669281 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/669281
Programmable memory address decode array with vertical transistors Sep 25, 2000 Issued
Array ( [id] => 1520647 [patent_doc_number] => 06413813 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Method for making DRAM using an oxide plug in the bitline contacts during fabrication' [patent_app_type] => B1 [patent_app_number] => 09/668131 [patent_app_country] => US [patent_app_date] => 2000-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 2918 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/413/06413813.pdf [firstpage_image] =>[orig_patent_app_number] => 09668131 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/668131
Method for making DRAM using an oxide plug in the bitline contacts during fabrication Sep 21, 2000 Issued
Array ( [id] => 1403335 [patent_doc_number] => 06541809 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-01 [patent_title] => 'Method of making straight wall containers and the resultant containers' [patent_app_type] => B1 [patent_app_number] => 09/662314 [patent_app_country] => US [patent_app_date] => 2000-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4135 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/541/06541809.pdf [firstpage_image] =>[orig_patent_app_number] => 09662314 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/662314
Method of making straight wall containers and the resultant containers Sep 13, 2000 Issued
Array ( [id] => 1303146 [patent_doc_number] => 06620739 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-16 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/657620 [patent_app_country] => US [patent_app_date] => 2000-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 4 [patent_no_of_words] => 5532 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/620/06620739.pdf [firstpage_image] =>[orig_patent_app_number] => 09657620 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/657620
Method of manufacturing semiconductor device Sep 7, 2000 Issued
Array ( [id] => 1503362 [patent_doc_number] => 06465283 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Structure and fabrication method using latch-up implantation for improving latch-up immunity in CMOS fabrication process' [patent_app_type] => B1 [patent_app_number] => 09/654810 [patent_app_country] => US [patent_app_date] => 2000-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 3449 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/465/06465283.pdf [firstpage_image] =>[orig_patent_app_number] => 09654810 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/654810
Structure and fabrication method using latch-up implantation for improving latch-up immunity in CMOS fabrication process Sep 4, 2000 Issued
Array ( [id] => 1503602 [patent_doc_number] => 06465331 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'DRAM fabricated on a silicon-on-insulator (SOI) substrate having bi-level digit lines' [patent_app_type] => B1 [patent_app_number] => 09/655000 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 4639 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/465/06465331.pdf [firstpage_image] =>[orig_patent_app_number] => 09655000 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/655000
DRAM fabricated on a silicon-on-insulator (SOI) substrate having bi-level digit lines Aug 30, 2000 Issued
Array ( [id] => 1183169 [patent_doc_number] => 06737730 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-18 [patent_title] => 'High-pressure anneal process for integrated circuits' [patent_app_type] => B1 [patent_app_number] => 09/652921 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1845 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/737/06737730.pdf [firstpage_image] =>[orig_patent_app_number] => 09652921 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/652921
High-pressure anneal process for integrated circuits Aug 30, 2000 Issued
Array ( [id] => 1500355 [patent_doc_number] => 06486043 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'Method of forming dislocation filter in merged SOI and non-SOI chips' [patent_app_type] => B1 [patent_app_number] => 09/652711 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 1801 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/486/06486043.pdf [firstpage_image] =>[orig_patent_app_number] => 09652711 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/652711
Method of forming dislocation filter in merged SOI and non-SOI chips Aug 30, 2000 Issued
Array ( [id] => 1220654 [patent_doc_number] => 06703325 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-09 [patent_title] => 'High pressure anneal process for integrated circuits' [patent_app_type] => B1 [patent_app_number] => 09/654030 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1772 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/703/06703325.pdf [firstpage_image] =>[orig_patent_app_number] => 09654030 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/654030
High pressure anneal process for integrated circuits Aug 30, 2000 Issued
Array ( [id] => 1553463 [patent_doc_number] => 06348372 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'Method for reducing PN junction leakage' [patent_app_type] => B1 [patent_app_number] => 09/648867 [patent_app_country] => US [patent_app_date] => 2000-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3803 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/348/06348372.pdf [firstpage_image] =>[orig_patent_app_number] => 09648867 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/648867
Method for reducing PN junction leakage Aug 24, 2000 Issued
Array ( [id] => 1073702 [patent_doc_number] => 06838367 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-04 [patent_title] => 'Method for simultaneous formation of fuse and capacitor plate and resulting structure' [patent_app_type] => utility [patent_app_number] => 09/644700 [patent_app_country] => US [patent_app_date] => 2000-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3533 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/838/06838367.pdf [firstpage_image] =>[orig_patent_app_number] => 09644700 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/644700
Method for simultaneous formation of fuse and capacitor plate and resulting structure Aug 23, 2000 Issued
Array ( [id] => 1412467 [patent_doc_number] => 06524937 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Selective T-gate process' [patent_app_type] => B1 [patent_app_number] => 09/644131 [patent_app_country] => US [patent_app_date] => 2000-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3420 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/524/06524937.pdf [firstpage_image] =>[orig_patent_app_number] => 09644131 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/644131
Selective T-gate process Aug 22, 2000 Issued
Array ( [id] => 1494964 [patent_doc_number] => 06403456 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'T or T/Y gate formation using trim etch processing' [patent_app_type] => B1 [patent_app_number] => 09/643611 [patent_app_country] => US [patent_app_date] => 2000-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 4384 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/403/06403456.pdf [firstpage_image] =>[orig_patent_app_number] => 09643611 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/643611
T or T/Y gate formation using trim etch processing Aug 21, 2000 Issued
Array ( [id] => 7647078 [patent_doc_number] => 06476440 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Nonvolatile memory device and method of manufacturing the same' [patent_app_type] => B1 [patent_app_number] => 09/642591 [patent_app_country] => US [patent_app_date] => 2000-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 3395 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/476/06476440.pdf [firstpage_image] =>[orig_patent_app_number] => 09642591 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/642591
Nonvolatile memory device and method of manufacturing the same Aug 21, 2000 Issued
Array ( [id] => 1389054 [patent_doc_number] => 06544801 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-08 [patent_title] => 'Method of fabricating thermally stable MTJ cell and apparatus' [patent_app_type] => B1 [patent_app_number] => 09/642350 [patent_app_country] => US [patent_app_date] => 2000-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 4071 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/544/06544801.pdf [firstpage_image] =>[orig_patent_app_number] => 09642350 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/642350
Method of fabricating thermally stable MTJ cell and apparatus Aug 20, 2000 Issued
Array ( [id] => 1449950 [patent_doc_number] => 06455372 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Nucleation for improved flash erase characteristics' [patent_app_type] => B1 [patent_app_number] => 09/639580 [patent_app_country] => US [patent_app_date] => 2000-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4558 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/455/06455372.pdf [firstpage_image] =>[orig_patent_app_number] => 09639580 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/639580
Nucleation for improved flash erase characteristics Aug 13, 2000 Issued
Array ( [id] => 1585379 [patent_doc_number] => 06358782 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Method of fabricating a semiconductor device having a silicon-on-insulator substrate and an independent metal electrode connected to the support substrate' [patent_app_type] => B1 [patent_app_number] => 09/635690 [patent_app_country] => US [patent_app_date] => 2000-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 36 [patent_no_of_words] => 11427 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 338 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/358/06358782.pdf [firstpage_image] =>[orig_patent_app_number] => 09635690 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/635690
Method of fabricating a semiconductor device having a silicon-on-insulator substrate and an independent metal electrode connected to the support substrate Aug 9, 2000 Issued
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