
Lalrinfamkim Hmar Malsawma
Examiner (ID: 2370)
| Most Active Art Unit | 2892 |
| Art Unit(s) | 2823, 2892, 2825 |
| Total Applications | 1951 |
| Issued Applications | 1709 |
| Pending Applications | 105 |
| Abandoned Applications | 179 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1486773
[patent_doc_number] => 06365954
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-02
[patent_title] => 'Metal-polycrystalline silicon-n-well multiple layered capacitor'
[patent_app_type] => B1
[patent_app_number] => 09/679513
[patent_app_country] => US
[patent_app_date] => 2000-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 3842
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/365/06365954.pdf
[firstpage_image] =>[orig_patent_app_number] => 09679513
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/679513 | Metal-polycrystalline silicon-n-well multiple layered capacitor | Oct 5, 2000 | Issued |
Array
(
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[patent_doc_number] => 06451693
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-17
[patent_title] => 'Double silicide formation in polysicon gate without silicide in source/drain extensions'
[patent_app_type] => B1
[patent_app_number] => 09/679370
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[patent_app_date] => 2000-10-05
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[firstpage_image] =>[orig_patent_app_number] => 09679370
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/679370 | Double silicide formation in polysicon gate without silicide in source/drain extensions | Oct 4, 2000 | Issued |
Array
(
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[patent_doc_number] => 06514835
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-02-04
[patent_title] => 'Stress control of thin films by mechanical deformation of wafer substrate'
[patent_app_type] => B1
[patent_app_number] => 09/676283
[patent_app_country] => US
[patent_app_date] => 2000-09-28
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/676283 | Stress control of thin films by mechanical deformation of wafer substrate | Sep 27, 2000 | Issued |
Array
(
[id] => 1336585
[patent_doc_number] => 06597037
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-07-22
[patent_title] => 'Programmable memory address decode array with vertical transistors'
[patent_app_type] => B1
[patent_app_number] => 09/669281
[patent_app_country] => US
[patent_app_date] => 2000-09-26
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/597/06597037.pdf
[firstpage_image] =>[orig_patent_app_number] => 09669281
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/669281 | Programmable memory address decode array with vertical transistors | Sep 25, 2000 | Issued |
Array
(
[id] => 1520647
[patent_doc_number] => 06413813
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-02
[patent_title] => 'Method for making DRAM using an oxide plug in the bitline contacts during fabrication'
[patent_app_type] => B1
[patent_app_number] => 09/668131
[patent_app_country] => US
[patent_app_date] => 2000-09-22
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[pdf_file] => patents/06/413/06413813.pdf
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Array
(
[id] => 1403335
[patent_doc_number] => 06541809
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-01
[patent_title] => 'Method of making straight wall containers and the resultant containers'
[patent_app_type] => B1
[patent_app_number] => 09/662314
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[patent_app_date] => 2000-09-14
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[firstpage_image] =>[orig_patent_app_number] => 09662314
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/662314 | Method of making straight wall containers and the resultant containers | Sep 13, 2000 | Issued |
Array
(
[id] => 1303146
[patent_doc_number] => 06620739
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[patent_kind] => B1
[patent_issue_date] => 2003-09-16
[patent_title] => 'Method of manufacturing semiconductor device'
[patent_app_type] => B1
[patent_app_number] => 09/657620
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/657620 | Method of manufacturing semiconductor device | Sep 7, 2000 | Issued |
Array
(
[id] => 1503362
[patent_doc_number] => 06465283
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[patent_kind] => B1
[patent_issue_date] => 2002-10-15
[patent_title] => 'Structure and fabrication method using latch-up implantation for improving latch-up immunity in CMOS fabrication process'
[patent_app_type] => B1
[patent_app_number] => 09/654810
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/654810 | Structure and fabrication method using latch-up implantation for improving latch-up immunity in CMOS fabrication process | Sep 4, 2000 | Issued |
Array
(
[id] => 1503602
[patent_doc_number] => 06465331
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-10-15
[patent_title] => 'DRAM fabricated on a silicon-on-insulator (SOI) substrate having bi-level digit lines'
[patent_app_type] => B1
[patent_app_number] => 09/655000
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/655000 | DRAM fabricated on a silicon-on-insulator (SOI) substrate having bi-level digit lines | Aug 30, 2000 | Issued |
Array
(
[id] => 1183169
[patent_doc_number] => 06737730
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[patent_kind] => B1
[patent_issue_date] => 2004-05-18
[patent_title] => 'High-pressure anneal process for integrated circuits'
[patent_app_type] => B1
[patent_app_number] => 09/652921
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[patent_app_date] => 2000-08-31
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/652921 | High-pressure anneal process for integrated circuits | Aug 30, 2000 | Issued |
Array
(
[id] => 1500355
[patent_doc_number] => 06486043
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[patent_issue_date] => 2002-11-26
[patent_title] => 'Method of forming dislocation filter in merged SOI and non-SOI chips'
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[patent_app_number] => 09/652711
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Array
(
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[patent_title] => 'High pressure anneal process for integrated circuits'
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Array
(
[id] => 1553463
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[patent_issue_date] => 2002-02-19
[patent_title] => 'Method for reducing PN junction leakage'
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Array
(
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[patent_issue_date] => 2005-01-04
[patent_title] => 'Method for simultaneous formation of fuse and capacitor plate and resulting structure'
[patent_app_type] => utility
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Array
(
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Array
(
[id] => 1494964
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Array
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Array
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Array
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Array
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