Search

Lalrinfamkim Hmar Malsawma

Examiner (ID: 5479)

Most Active Art Unit
2892
Art Unit(s)
2825, 2892, 2823
Total Applications
2001
Issued Applications
1735
Pending Applications
112
Abandoned Applications
179

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1474382 [patent_doc_number] => 06387728 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Method for fabricating a stacked chip package' [patent_app_type] => B1 [patent_app_number] => 09/562910 [patent_app_country] => US [patent_app_date] => 2000-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2269 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/387/06387728.pdf [firstpage_image] =>[orig_patent_app_number] => 09562910 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/562910
Method for fabricating a stacked chip package May 1, 2000 Issued
Array ( [id] => 6668981 [patent_doc_number] => 20030113965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-19 [patent_title] => 'METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE' [patent_app_type] => new [patent_app_number] => 09/553331 [patent_app_country] => US [patent_app_date] => 2000-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4826 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20030113965.pdf [firstpage_image] =>[orig_patent_app_number] => 09553331 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/553331
Method of manufacturing a semiconductor device Apr 19, 2000 Issued
Array ( [id] => 4336428 [patent_doc_number] => 06333235 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-25 [patent_title] => 'Method for forming SiGe bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 9/547871 [patent_app_country] => US [patent_app_date] => 2000-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 22 [patent_no_of_words] => 5010 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 741 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/333/06333235.pdf [firstpage_image] =>[orig_patent_app_number] => 547871 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/547871
Method for forming SiGe bipolar transistor Apr 11, 2000 Issued
Array ( [id] => 1399565 [patent_doc_number] => 06545318 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-08 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => B1 [patent_app_number] => 09/548311 [patent_app_country] => US [patent_app_date] => 2000-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 28 [patent_no_of_words] => 14294 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/545/06545318.pdf [firstpage_image] =>[orig_patent_app_number] => 09548311 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/548311
Semiconductor device and manufacturing method thereof Apr 11, 2000 Issued
Array ( [id] => 1277857 [patent_doc_number] => 06645833 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-11 [patent_title] => 'Method for producing layered structures on a substrate, substrate and semiconductor components produced according to said method' [patent_app_type] => B2 [patent_app_number] => 09/447000 [patent_app_country] => US [patent_app_date] => 2000-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 43 [patent_no_of_words] => 13673 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/645/06645833.pdf [firstpage_image] =>[orig_patent_app_number] => 09447000 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/447000
Method for producing layered structures on a substrate, substrate and semiconductor components produced according to said method Apr 6, 2000 Issued
Array ( [id] => 4327714 [patent_doc_number] => 06319844 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Method of manufacturing semiconductor device with via holes reaching interconnect layers having different top-surface widths' [patent_app_type] => 1 [patent_app_number] => 9/544490 [patent_app_country] => US [patent_app_date] => 2000-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3144 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/319/06319844.pdf [firstpage_image] =>[orig_patent_app_number] => 544490 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/544490
Method of manufacturing semiconductor device with via holes reaching interconnect layers having different top-surface widths Apr 6, 2000 Issued
Array ( [id] => 1485140 [patent_doc_number] => 06365443 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Method of manufacturing a semiconductor device having data pads formed in scribed area' [patent_app_type] => B1 [patent_app_number] => 09/538231 [patent_app_country] => US [patent_app_date] => 2000-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 28 [patent_no_of_words] => 6861 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/365/06365443.pdf [firstpage_image] =>[orig_patent_app_number] => 09538231 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/538231
Method of manufacturing a semiconductor device having data pads formed in scribed area Mar 29, 2000 Issued
Array ( [id] => 1536092 [patent_doc_number] => 06337251 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-08 [patent_title] => 'Method of manufacturing semiconductor device with no parasitic barrier' [patent_app_type] => B1 [patent_app_number] => 09/538290 [patent_app_country] => US [patent_app_date] => 2000-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2657 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/337/06337251.pdf [firstpage_image] =>[orig_patent_app_number] => 09538290 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/538290
Method of manufacturing semiconductor device with no parasitic barrier Mar 28, 2000 Issued
Array ( [id] => 4336476 [patent_doc_number] => 06333237 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-25 [patent_title] => 'Method for manufacturing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/531690 [patent_app_country] => US [patent_app_date] => 2000-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 27 [patent_no_of_words] => 5880 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 436 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/333/06333237.pdf [firstpage_image] =>[orig_patent_app_number] => 531690 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/531690
Method for manufacturing a semiconductor device Mar 19, 2000 Issued
Array ( [id] => 1504708 [patent_doc_number] => 06439969 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Apparatus and method of chamfering wafer' [patent_app_type] => B1 [patent_app_number] => 09/522910 [patent_app_country] => US [patent_app_date] => 2000-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 8442 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 956 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/439/06439969.pdf [firstpage_image] =>[orig_patent_app_number] => 09522910 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/522910
Apparatus and method of chamfering wafer Mar 9, 2000 Issued
Array ( [id] => 4420393 [patent_doc_number] => 06225196 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'High electron mobility transistor and method of fabricating the same' [patent_app_type] => 1 [patent_app_number] => 9/521781 [patent_app_country] => US [patent_app_date] => 2000-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 19 [patent_no_of_words] => 6624 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225196.pdf [firstpage_image] =>[orig_patent_app_number] => 521781 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/521781
High electron mobility transistor and method of fabricating the same Mar 8, 2000 Issued
Array ( [id] => 1310826 [patent_doc_number] => 06613671 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-02 [patent_title] => 'Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby' [patent_app_type] => B1 [patent_app_number] => 09/518511 [patent_app_country] => US [patent_app_date] => 2000-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 4075 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/613/06613671.pdf [firstpage_image] =>[orig_patent_app_number] => 09518511 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/518511
Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby Mar 2, 2000 Issued
09/486601 METHOD OF FORMING SINGLE-CRYSTAL SILICON LAYER AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Feb 28, 2000 Abandoned
Array ( [id] => 1327353 [patent_doc_number] => 06599837 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-29 [patent_title] => 'Chemical mechanical polishing composition and method of polishing metal layers using same' [patent_app_type] => B1 [patent_app_number] => 09/515730 [patent_app_country] => US [patent_app_date] => 2000-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2909 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/599/06599837.pdf [firstpage_image] =>[orig_patent_app_number] => 09515730 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/515730
Chemical mechanical polishing composition and method of polishing metal layers using same Feb 28, 2000 Issued
Array ( [id] => 1559221 [patent_doc_number] => 06374484 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Parts mounting method and apparatus' [patent_app_type] => B1 [patent_app_number] => 09/486661 [patent_app_country] => US [patent_app_date] => 2000-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 14598 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 319 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/374/06374484.pdf [firstpage_image] =>[orig_patent_app_number] => 09486661 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/486661
Parts mounting method and apparatus Feb 27, 2000 Issued
Array ( [id] => 4380852 [patent_doc_number] => 06277683 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Method of forming a sidewall spacer and a salicide blocking shape, using only one silicon nitride layer' [patent_app_type] => 1 [patent_app_number] => 9/514900 [patent_app_country] => US [patent_app_date] => 2000-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2509 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 502 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/277/06277683.pdf [firstpage_image] =>[orig_patent_app_number] => 514900 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/514900
Method of forming a sidewall spacer and a salicide blocking shape, using only one silicon nitride layer Feb 27, 2000 Issued
Array ( [id] => 1414873 [patent_doc_number] => 06511855 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-28 [patent_title] => 'Method of forming ferromagnetic tunnel junctions with enhanced magneto-resistance' [patent_app_type] => B2 [patent_app_number] => 09/672794 [patent_app_country] => US [patent_app_date] => 2000-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2502 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/511/06511855.pdf [firstpage_image] =>[orig_patent_app_number] => 09672794 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/672794
Method of forming ferromagnetic tunnel junctions with enhanced magneto-resistance Feb 10, 2000 Issued
Array ( [id] => 1594610 [patent_doc_number] => 06383925 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Method of improving adhesion of capping layers to cooper interconnects' [patent_app_type] => B1 [patent_app_number] => 09/497850 [patent_app_country] => US [patent_app_date] => 2000-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3510 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/383/06383925.pdf [firstpage_image] =>[orig_patent_app_number] => 09497850 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/497850
Method of improving adhesion of capping layers to cooper interconnects Feb 3, 2000 Issued
Array ( [id] => 4312556 [patent_doc_number] => 06242319 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Method for fabricating an integrated circuit configuration' [patent_app_type] => 1 [patent_app_number] => 9/498530 [patent_app_country] => US [patent_app_date] => 2000-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3647 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/242/06242319.pdf [firstpage_image] =>[orig_patent_app_number] => 498530 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/498530
Method for fabricating an integrated circuit configuration Feb 3, 2000 Issued
Array ( [id] => 4326476 [patent_doc_number] => 06319763 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Manufacturing method for semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/497500 [patent_app_country] => US [patent_app_date] => 2000-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 5108 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/319/06319763.pdf [firstpage_image] =>[orig_patent_app_number] => 497500 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/497500
Manufacturing method for semiconductor device Feb 3, 2000 Issued
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