
Lalrinfamkim Hmar Malsawma
Examiner (ID: 2370)
| Most Active Art Unit | 2892 |
| Art Unit(s) | 2823, 2892, 2825 |
| Total Applications | 1951 |
| Issued Applications | 1709 |
| Pending Applications | 105 |
| Abandoned Applications | 179 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4327714
[patent_doc_number] => 06319844
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-20
[patent_title] => 'Method of manufacturing semiconductor device with via holes reaching interconnect layers having different top-surface widths'
[patent_app_type] => 1
[patent_app_number] => 9/544490
[patent_app_country] => US
[patent_app_date] => 2000-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 3144
[patent_no_of_claims] => 19
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[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/319/06319844.pdf
[firstpage_image] =>[orig_patent_app_number] => 544490
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/544490 | Method of manufacturing semiconductor device with via holes reaching interconnect layers having different top-surface widths | Apr 6, 2000 | Issued |
Array
(
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[patent_doc_number] => 06645833
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-11-11
[patent_title] => 'Method for producing layered structures on a substrate, substrate and semiconductor components produced according to said method'
[patent_app_type] => B2
[patent_app_number] => 09/447000
[patent_app_country] => US
[patent_app_date] => 2000-04-07
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[patent_no_of_words] => 13673
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[pdf_file] => patents/06/645/06645833.pdf
[firstpage_image] =>[orig_patent_app_number] => 09447000
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/447000 | Method for producing layered structures on a substrate, substrate and semiconductor components produced according to said method | Apr 6, 2000 | Issued |
Array
(
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[patent_doc_number] => 06365443
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[patent_kind] => B1
[patent_issue_date] => 2002-04-02
[patent_title] => 'Method of manufacturing a semiconductor device having data pads formed in scribed area'
[patent_app_type] => B1
[patent_app_number] => 09/538231
[patent_app_country] => US
[patent_app_date] => 2000-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
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[pdf_file] => patents/06/365/06365443.pdf
[firstpage_image] =>[orig_patent_app_number] => 09538231
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/538231 | Method of manufacturing a semiconductor device having data pads formed in scribed area | Mar 29, 2000 | Issued |
Array
(
[id] => 1536092
[patent_doc_number] => 06337251
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-01-08
[patent_title] => 'Method of manufacturing semiconductor device with no parasitic barrier'
[patent_app_type] => B1
[patent_app_number] => 09/538290
[patent_app_country] => US
[patent_app_date] => 2000-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 2657
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/337/06337251.pdf
[firstpage_image] =>[orig_patent_app_number] => 09538290
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/538290 | Method of manufacturing semiconductor device with no parasitic barrier | Mar 28, 2000 | Issued |
Array
(
[id] => 4336476
[patent_doc_number] => 06333237
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-12-25
[patent_title] => 'Method for manufacturing a semiconductor device'
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[patent_app_number] => 9/531690
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[pdf_file] => patents/06/333/06333237.pdf
[firstpage_image] =>[orig_patent_app_number] => 531690
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/531690 | Method for manufacturing a semiconductor device | Mar 19, 2000 | Issued |
Array
(
[id] => 1504708
[patent_doc_number] => 06439969
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-27
[patent_title] => 'Apparatus and method of chamfering wafer'
[patent_app_type] => B1
[patent_app_number] => 09/522910
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[patent_app_date] => 2000-03-10
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[firstpage_image] =>[orig_patent_app_number] => 09522910
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/522910 | Apparatus and method of chamfering wafer | Mar 9, 2000 | Issued |
Array
(
[id] => 4420393
[patent_doc_number] => 06225196
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-01
[patent_title] => 'High electron mobility transistor and method of fabricating the same'
[patent_app_type] => 1
[patent_app_number] => 9/521781
[patent_app_country] => US
[patent_app_date] => 2000-03-09
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 6624
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[pdf_file] => patents/06/225/06225196.pdf
[firstpage_image] =>[orig_patent_app_number] => 521781
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/521781 | High electron mobility transistor and method of fabricating the same | Mar 8, 2000 | Issued |
Array
(
[id] => 1310826
[patent_doc_number] => 06613671
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-09-02
[patent_title] => 'Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby'
[patent_app_type] => B1
[patent_app_number] => 09/518511
[patent_app_country] => US
[patent_app_date] => 2000-03-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 4075
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[pdf_file] => patents/06/613/06613671.pdf
[firstpage_image] =>[orig_patent_app_number] => 09518511
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/518511 | Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby | Mar 2, 2000 | Issued |
Array
(
[id] => 1327353
[patent_doc_number] => 06599837
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-07-29
[patent_title] => 'Chemical mechanical polishing composition and method of polishing metal layers using same'
[patent_app_type] => B1
[patent_app_number] => 09/515730
[patent_app_country] => US
[patent_app_date] => 2000-02-29
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[pdf_file] => patents/06/599/06599837.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/515730 | Chemical mechanical polishing composition and method of polishing metal layers using same | Feb 28, 2000 | Issued |
| 09/486601 | METHOD OF FORMING SINGLE-CRYSTAL SILICON LAYER AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE | Feb 28, 2000 | Abandoned |
Array
(
[id] => 1559221
[patent_doc_number] => 06374484
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-23
[patent_title] => 'Parts mounting method and apparatus'
[patent_app_type] => B1
[patent_app_number] => 09/486661
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 09486661
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/486661 | Parts mounting method and apparatus | Feb 27, 2000 | Issued |
Array
(
[id] => 4380852
[patent_doc_number] => 06277683
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-21
[patent_title] => 'Method of forming a sidewall spacer and a salicide blocking shape, using only one silicon nitride layer'
[patent_app_type] => 1
[patent_app_number] => 9/514900
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Array
(
[id] => 1414873
[patent_doc_number] => 06511855
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-01-28
[patent_title] => 'Method of forming ferromagnetic tunnel junctions with enhanced magneto-resistance'
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Array
(
[id] => 4326476
[patent_doc_number] => 06319763
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[patent_issue_date] => 2001-11-20
[patent_title] => 'Manufacturing method for semiconductor device'
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[firstpage_image] =>[orig_patent_app_number] => 497500
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/497500 | Manufacturing method for semiconductor device | Feb 3, 2000 | Issued |
Array
(
[id] => 4312556
[patent_doc_number] => 06242319
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[patent_kind] => NA
[patent_issue_date] => 2001-06-05
[patent_title] => 'Method for fabricating an integrated circuit configuration'
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Array
(
[id] => 1594610
[patent_doc_number] => 06383925
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[patent_issue_date] => 2002-05-07
[patent_title] => 'Method of improving adhesion of capping layers to cooper interconnects'
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Array
(
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[patent_title] => 'Substrate and method of manufacturing the same'
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Array
(
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[patent_issue_date] => 2001-09-18
[patent_title] => 'Method of fabricating gate structure to reduce stress production'
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Array
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[patent_title] => 'Method to resolve the passivation surface roughness during formation of the AlCu pad for the copper process'
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Array
(
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[patent_title] => 'Two-level silane nucleation for blanket tungsten deposition'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/489510 | Two-level silane nucleation for blanket tungsten deposition | Jan 20, 2000 | Issued |