
Lalrinfamkim Hmar Malsawma
Examiner (ID: 5479)
| Most Active Art Unit | 2892 |
| Art Unit(s) | 2825, 2892, 2823 |
| Total Applications | 2001 |
| Issued Applications | 1735 |
| Pending Applications | 112 |
| Abandoned Applications | 179 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1474382
[patent_doc_number] => 06387728
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-05-14
[patent_title] => 'Method for fabricating a stacked chip package'
[patent_app_type] => B1
[patent_app_number] => 09/562910
[patent_app_country] => US
[patent_app_date] => 2000-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 2269
[patent_no_of_claims] => 10
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[patent_words_short_claim] => 137
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/387/06387728.pdf
[firstpage_image] =>[orig_patent_app_number] => 09562910
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/562910 | Method for fabricating a stacked chip package | May 1, 2000 | Issued |
Array
(
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[patent_doc_number] => 20030113965
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-06-19
[patent_title] => 'METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE'
[patent_app_type] => new
[patent_app_number] => 09/553331
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[patent_app_date] => 2000-04-20
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[patent_no_of_words] => 4826
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[pdf_file] => publications/A1/0113/20030113965.pdf
[firstpage_image] =>[orig_patent_app_number] => 09553331
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/553331 | Method of manufacturing a semiconductor device | Apr 19, 2000 | Issued |
Array
(
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[patent_kind] => NA
[patent_issue_date] => 2001-12-25
[patent_title] => 'Method for forming SiGe bipolar transistor'
[patent_app_type] => 1
[patent_app_number] => 9/547871
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[patent_app_date] => 2000-04-12
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/547871 | Method for forming SiGe bipolar transistor | Apr 11, 2000 | Issued |
Array
(
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[patent_doc_number] => 06545318
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[patent_issue_date] => 2003-04-08
[patent_title] => 'Semiconductor device and manufacturing method thereof'
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[patent_app_number] => 09/548311
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/548311 | Semiconductor device and manufacturing method thereof | Apr 11, 2000 | Issued |
Array
(
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[patent_doc_number] => 06645833
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[patent_issue_date] => 2003-11-11
[patent_title] => 'Method for producing layered structures on a substrate, substrate and semiconductor components produced according to said method'
[patent_app_type] => B2
[patent_app_number] => 09/447000
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[pdf_file] => patents/06/645/06645833.pdf
[firstpage_image] =>[orig_patent_app_number] => 09447000
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/447000 | Method for producing layered structures on a substrate, substrate and semiconductor components produced according to said method | Apr 6, 2000 | Issued |
Array
(
[id] => 4327714
[patent_doc_number] => 06319844
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[patent_issue_date] => 2001-11-20
[patent_title] => 'Method of manufacturing semiconductor device with via holes reaching interconnect layers having different top-surface widths'
[patent_app_type] => 1
[patent_app_number] => 9/544490
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Array
(
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[patent_issue_date] => 2002-04-02
[patent_title] => 'Method of manufacturing a semiconductor device having data pads formed in scribed area'
[patent_app_type] => B1
[patent_app_number] => 09/538231
[patent_app_country] => US
[patent_app_date] => 2000-03-30
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/538231 | Method of manufacturing a semiconductor device having data pads formed in scribed area | Mar 29, 2000 | Issued |
Array
(
[id] => 1536092
[patent_doc_number] => 06337251
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[patent_issue_date] => 2002-01-08
[patent_title] => 'Method of manufacturing semiconductor device with no parasitic barrier'
[patent_app_type] => B1
[patent_app_number] => 09/538290
[patent_app_country] => US
[patent_app_date] => 2000-03-29
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/538290 | Method of manufacturing semiconductor device with no parasitic barrier | Mar 28, 2000 | Issued |
Array
(
[id] => 4336476
[patent_doc_number] => 06333237
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[patent_kind] => NA
[patent_issue_date] => 2001-12-25
[patent_title] => 'Method for manufacturing a semiconductor device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/531690 | Method for manufacturing a semiconductor device | Mar 19, 2000 | Issued |
Array
(
[id] => 1504708
[patent_doc_number] => 06439969
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[patent_issue_date] => 2002-08-27
[patent_title] => 'Apparatus and method of chamfering wafer'
[patent_app_type] => B1
[patent_app_number] => 09/522910
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/522910 | Apparatus and method of chamfering wafer | Mar 9, 2000 | Issued |
Array
(
[id] => 4420393
[patent_doc_number] => 06225196
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-01
[patent_title] => 'High electron mobility transistor and method of fabricating the same'
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[patent_app_number] => 9/521781
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[firstpage_image] =>[orig_patent_app_number] => 521781
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/521781 | High electron mobility transistor and method of fabricating the same | Mar 8, 2000 | Issued |
Array
(
[id] => 1310826
[patent_doc_number] => 06613671
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[patent_issue_date] => 2003-09-02
[patent_title] => 'Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/518511 | Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby | Mar 2, 2000 | Issued |
| 09/486601 | METHOD OF FORMING SINGLE-CRYSTAL SILICON LAYER AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE | Feb 28, 2000 | Abandoned |
Array
(
[id] => 1327353
[patent_doc_number] => 06599837
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[patent_issue_date] => 2003-07-29
[patent_title] => 'Chemical mechanical polishing composition and method of polishing metal layers using same'
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Array
(
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[patent_title] => 'Parts mounting method and apparatus'
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Array
(
[id] => 4380852
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[patent_issue_date] => 2001-08-21
[patent_title] => 'Method of forming a sidewall spacer and a salicide blocking shape, using only one silicon nitride layer'
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Array
(
[id] => 1414873
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[patent_title] => 'Method of forming ferromagnetic tunnel junctions with enhanced magneto-resistance'
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Array
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Array
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Array
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