Search

Lalrinfamkim Hmar Malsawma

Examiner (ID: 2370)

Most Active Art Unit
2892
Art Unit(s)
2823, 2892, 2825
Total Applications
1951
Issued Applications
1709
Pending Applications
105
Abandoned Applications
179

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1409686 [patent_doc_number] => 06534796 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-18 [patent_title] => 'Integrated circuit optics assembly unit' [patent_app_type] => B1 [patent_app_number] => 09/408810 [patent_app_country] => US [patent_app_date] => 1999-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3724 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/534/06534796.pdf [firstpage_image] =>[orig_patent_app_number] => 09408810 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/408810
Integrated circuit optics assembly unit Sep 28, 1999 Issued
Array ( [id] => 4246879 [patent_doc_number] => 06221717 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'EEPROM memory cell comprising a selection transistor with threshold voltage adjusted by implantation, and related manufacturing process' [patent_app_type] => 1 [patent_app_number] => 9/406879 [patent_app_country] => US [patent_app_date] => 1999-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 2132 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/221/06221717.pdf [firstpage_image] =>[orig_patent_app_number] => 406879 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/406879
EEPROM memory cell comprising a selection transistor with threshold voltage adjusted by implantation, and related manufacturing process Sep 27, 1999 Issued
Array ( [id] => 4249278 [patent_doc_number] => 06207471 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Method of producing solar cell device' [patent_app_type] => 1 [patent_app_number] => 9/381800 [patent_app_country] => US [patent_app_date] => 1999-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 4895 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/207/06207471.pdf [firstpage_image] =>[orig_patent_app_number] => 381800 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/381800
Method of producing solar cell device Sep 23, 1999 Issued
09/405456 METHOD OF FABRICATING A THREE-DIMENSIONAL SYSTEM-ON-CHIP AND ITS STRUCTURE Sep 23, 1999 Abandoned
Array ( [id] => 1235575 [patent_doc_number] => 06689634 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-10 [patent_title] => 'Modeling technique for selectively depopulating electrical contacts from a foot print of a grid array (BGA or LGA) package to increase device reliability' [patent_app_type] => B1 [patent_app_number] => 09/400811 [patent_app_country] => US [patent_app_date] => 1999-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 7148 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/689/06689634.pdf [firstpage_image] =>[orig_patent_app_number] => 09400811 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/400811
Modeling technique for selectively depopulating electrical contacts from a foot print of a grid array (BGA or LGA) package to increase device reliability Sep 21, 1999 Issued
Array ( [id] => 4373562 [patent_doc_number] => 06274931 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Integrated circuit packaging systems and methods that use the same packaging substrates for integrated circuits of different data path widths' [patent_app_type] => 1 [patent_app_number] => 9/395649 [patent_app_country] => US [patent_app_date] => 1999-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4263 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/274/06274931.pdf [firstpage_image] =>[orig_patent_app_number] => 395649 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/395649
Integrated circuit packaging systems and methods that use the same packaging substrates for integrated circuits of different data path widths Sep 13, 1999 Issued
Array ( [id] => 4381842 [patent_doc_number] => 06277749 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Method of manufacturing a semiconductor integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 9/392568 [patent_app_country] => US [patent_app_date] => 1999-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 5731 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/277/06277749.pdf [firstpage_image] =>[orig_patent_app_number] => 392568 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/392568
Method of manufacturing a semiconductor integrated circuit device Sep 8, 1999 Issued
Array ( [id] => 4186421 [patent_doc_number] => 06093661 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Integrated circuitry and semiconductor processing method of forming field effect transistors' [patent_app_type] => 1 [patent_app_number] => 9/386076 [patent_app_country] => US [patent_app_date] => 1999-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3322 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/093/06093661.pdf [firstpage_image] =>[orig_patent_app_number] => 386076 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/386076
Integrated circuitry and semiconductor processing method of forming field effect transistors Aug 29, 1999 Issued
Array ( [id] => 1413048 [patent_doc_number] => 06553555 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Maintaining signal guard bands when routing through a field of obstacles' [patent_app_type] => B1 [patent_app_number] => 09/384172 [patent_app_country] => US [patent_app_date] => 1999-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3747 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/553/06553555.pdf [firstpage_image] =>[orig_patent_app_number] => 09384172 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/384172
Maintaining signal guard bands when routing through a field of obstacles Aug 26, 1999 Issued
Array ( [id] => 4258330 [patent_doc_number] => 06204128 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/383418 [patent_app_country] => US [patent_app_date] => 1999-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 61 [patent_no_of_words] => 12358 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/204/06204128.pdf [firstpage_image] =>[orig_patent_app_number] => 383418 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/383418
Method for fabricating semiconductor device Aug 25, 1999 Issued
Array ( [id] => 4358895 [patent_doc_number] => 06291859 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/377829 [patent_app_country] => US [patent_app_date] => 1999-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1333 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/291/06291859.pdf [firstpage_image] =>[orig_patent_app_number] => 377829 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/377829
Integrated circuits Aug 19, 1999 Issued
Array ( [id] => 4259118 [patent_doc_number] => 06258685 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Method of manufacturing hetero-junction bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 9/376299 [patent_app_country] => US [patent_app_date] => 1999-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 6358 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/258/06258685.pdf [firstpage_image] =>[orig_patent_app_number] => 376299 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/376299
Method of manufacturing hetero-junction bipolar transistor Aug 17, 1999 Issued
Array ( [id] => 1542497 [patent_doc_number] => 06372558 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Electrooptic device, driving substrate for electrooptic device, and method of manufacturing the device and substrate' [patent_app_type] => B1 [patent_app_number] => 09/376840 [patent_app_country] => US [patent_app_date] => 1999-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 75 [patent_figures_cnt] => 190 [patent_no_of_words] => 25348 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/372/06372558.pdf [firstpage_image] =>[orig_patent_app_number] => 09376840 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/376840
Electrooptic device, driving substrate for electrooptic device, and method of manufacturing the device and substrate Aug 17, 1999 Issued
Array ( [id] => 4252950 [patent_doc_number] => 06137126 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Method to reduce gate-to-local interconnect capacitance using a low dielectric constant material for LDD spacer' [patent_app_type] => 1 [patent_app_number] => 9/375499 [patent_app_country] => US [patent_app_date] => 1999-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1922 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137126.pdf [firstpage_image] =>[orig_patent_app_number] => 375499 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/375499
Method to reduce gate-to-local interconnect capacitance using a low dielectric constant material for LDD spacer Aug 16, 1999 Issued
Array ( [id] => 4235862 [patent_doc_number] => 06143635 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Field effect transistors with improved implants and method for making such transistors' [patent_app_type] => 1 [patent_app_number] => 9/374519 [patent_app_country] => US [patent_app_date] => 1999-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 5843 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/143/06143635.pdf [firstpage_image] =>[orig_patent_app_number] => 374519 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/374519
Field effect transistors with improved implants and method for making such transistors Aug 15, 1999 Issued
Array ( [id] => 4188197 [patent_doc_number] => 06153470 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Floating gate engineering to improve tunnel oxide reliability for flash memory devices' [patent_app_type] => 1 [patent_app_number] => 9/374059 [patent_app_country] => US [patent_app_date] => 1999-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3341 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/153/06153470.pdf [firstpage_image] =>[orig_patent_app_number] => 374059 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/374059
Floating gate engineering to improve tunnel oxide reliability for flash memory devices Aug 11, 1999 Issued
Array ( [id] => 4313213 [patent_doc_number] => 06242363 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Method of etching a wafer layer using a sacrificial wall to form vertical sidewall' [patent_app_type] => 1 [patent_app_number] => 9/372700 [patent_app_country] => US [patent_app_date] => 1999-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 3487 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/242/06242363.pdf [firstpage_image] =>[orig_patent_app_number] => 372700 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/372700
Method of etching a wafer layer using a sacrificial wall to form vertical sidewall Aug 10, 1999 Issued
Array ( [id] => 4360373 [patent_doc_number] => 06218689 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Method for providing a dopant level for polysilicon for flash memory devices' [patent_app_type] => 1 [patent_app_number] => 9/369638 [patent_app_country] => US [patent_app_date] => 1999-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3188 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218689.pdf [firstpage_image] =>[orig_patent_app_number] => 369638 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/369638
Method for providing a dopant level for polysilicon for flash memory devices Aug 5, 1999 Issued
Array ( [id] => 4094632 [patent_doc_number] => 06096604 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Production of reversed flash memory device' [patent_app_type] => 1 [patent_app_number] => 9/366739 [patent_app_country] => US [patent_app_date] => 1999-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 4442 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/096/06096604.pdf [firstpage_image] =>[orig_patent_app_number] => 366739 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/366739
Production of reversed flash memory device Aug 3, 1999 Issued
Array ( [id] => 4249694 [patent_doc_number] => 06207501 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Method of fabricating a flash memory' [patent_app_type] => 1 [patent_app_number] => 9/363879 [patent_app_country] => US [patent_app_date] => 1999-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 2641 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/207/06207501.pdf [firstpage_image] =>[orig_patent_app_number] => 363879 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/363879
Method of fabricating a flash memory Jul 28, 1999 Issued
Menu