Lalrinfamkim Hmar Malsawma

Array ( [id] => 4264716 [patent_doc_number] => 06204531 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Non-volatile memory structure and corresponding manufacturing process' [patent_app_type] => 1 [patent_app_number] => 9/363429 [patent_app_country] => US [patent_app_date] => 1999-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 25 [patent_no_of_words] => 3438 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/204/06204531.pdf [firstpage_image] =>[orig_patent_app_number] => 363429 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4406066 [patent_doc_number] => 06171932 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Semiconductor substrate and production method thereof' [patent_app_type] => 1 [patent_app_number] => 9/357979 [patent_app_country] => US [patent_app_date] => 1999-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 47 [patent_no_of_words] => 11479 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/171/06171932.pdf [firstpage_image] =>[orig_patent_app_number] => 357979 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4154178 [patent_doc_number] => 06103574 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Method of manufacturing non-volatile semiconductor memory device having reduced electrical resistance of a source diffusion layer' [patent_app_type] => 1 [patent_app_number] => 9/357958 [patent_app_country] => US [patent_app_date] => 1999-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 66 [patent_no_of_words] => 6073 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 428 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/103/06103574.pdf [firstpage_image] =>[orig_patent_app_number] => 357958 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4259746 [patent_doc_number] => 06258727 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Method of forming metal lands at the M0 level with a non selective chemistry' [patent_app_type] => 1 [patent_app_number] => 9/356970 [patent_app_country] => US [patent_app_date] => 1999-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3119 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/258/06258727.pdf [firstpage_image] =>[orig_patent_app_number] => 356970 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4293578 [patent_doc_number] => 06197639 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Method for manufacturing NOR-type flash memory device' [patent_app_type] => 1 [patent_app_number] => 9/352488 [patent_app_country] => US [patent_app_date] => 1999-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 3299 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/197/06197639.pdf [firstpage_image] =>[orig_patent_app_number] => 352488 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4357010 [patent_doc_number] => 06174772 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Optimal process flow of fabricating nitride spacer without inter-poly oxide damage in split gate flash' [patent_app_type] => 1 [patent_app_number] => 9/347548 [patent_app_country] => US [patent_app_date] => 1999-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 3022 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/174/06174772.pdf [firstpage_image] =>[orig_patent_app_number] => 347548 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4168696 [patent_doc_number] => 06140158 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Method of manufacturing thin film transistor-liquid crystal display' [patent_app_type] => 1 [patent_app_number] => 9/342609 [patent_app_country] => US [patent_app_date] => 1999-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 1447 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/140/06140158.pdf [firstpage_image] =>[orig_patent_app_number] => 342609 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4204644 [patent_doc_number] => 06077738 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Inter-level dielectric planarization approach for a DRAM crown capacitor process' [patent_app_type] => 1 [patent_app_number] => 9/344398 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 3075 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 319 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/077/06077738.pdf [firstpage_image] =>[orig_patent_app_number] => 344398 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6961297 [patent_doc_number] => 20010012656 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-09 [patent_title] => 'METHOD OF FORMING DRAM TRENCH CAPACITOR WITH METAL LAYER OVER HEMISPHERICAL GRAIN POLYSILICON' [patent_app_type] => new [patent_app_number] => 09/339890 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1982 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20010012656.pdf [firstpage_image] =>[orig_patent_app_number] => 09339890 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4378672 [patent_doc_number] => 06303510 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Plasma etch method with attenuated patterned layer charging' [patent_app_type] => 1 [patent_app_number] => 9/336810 [patent_app_country] => US [patent_app_date] => 1999-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 4934 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/303/06303510.pdf [firstpage_image] =>[orig_patent_app_number] => 336810 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4354034 [patent_doc_number] => 06218265 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Process for fabricating a semiconductor non-volatile memory device with shallow trench isolation (STI)' [patent_app_type] => 1 [patent_app_number] => 9/336089 [patent_app_country] => US [patent_app_date] => 1999-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 1961 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218265.pdf [firstpage_image] =>[orig_patent_app_number] => 336089 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6630638 [patent_doc_number] => 20020086503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'METHODS FOR FORMING WORDLINES, TRANSISTOR GATES, AND CONDUCTIVE INTERCONNECTS, AND WORDLINE, TRANSISTOR GATE, AND CONDUCTIVE INTERCONNECT STRUCTURES' [patent_app_type] => new [patent_app_number] => 09/333770 [patent_app_country] => US [patent_app_date] => 1999-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5577 [patent_no_of_claims] => 93 [patent_no_of_ind_claims] => 26 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20020086503.pdf [firstpage_image] =>[orig_patent_app_number] => 09333770 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4087231 [patent_doc_number] => 06133116 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Methods of forming trench isolation regions having conductive shields therein' [patent_app_type] => 1 [patent_app_number] => 9/328708 [patent_app_country] => US [patent_app_date] => 1999-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 31 [patent_no_of_words] => 3926 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/133/06133116.pdf [firstpage_image] =>[orig_patent_app_number] => 328708 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4249746 [patent_doc_number] => 06207505 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Method for forming high density nonvolatile memories with high capacitive-coupling ratio' [patent_app_type] => 1 [patent_app_number] => 9/326857 [patent_app_country] => US [patent_app_date] => 1999-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 2878 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/207/06207505.pdf [firstpage_image] =>[orig_patent_app_number] => 326857 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4414216 [patent_doc_number] => 06229182 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Semiconductor device having protection against electrostatic discharge' [patent_app_type] => 1 [patent_app_number] => 9/326894 [patent_app_country] => US [patent_app_date] => 1999-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3045 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/229/06229182.pdf [firstpage_image] =>[orig_patent_app_number] => 326894 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7636551 [patent_doc_number] => 06380105 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Low volatility solvent-based method for forming thin film nanoporous aerogels on semiconductor substrates' [patent_app_type] => B1 [patent_app_number] => 09/324370 [patent_app_country] => US [patent_app_date] => 1999-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 27 [patent_no_of_words] => 18116 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 16 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/380/06380105.pdf [firstpage_image] =>[orig_patent_app_number] => 09324370 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4254609 [patent_doc_number] => 06222237 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Structure of electrostatic discharge protection device' [patent_app_type] => 1 [patent_app_number] => 9/316584 [patent_app_country] => US [patent_app_date] => 1999-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1393 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/222/06222237.pdf [firstpage_image] =>[orig_patent_app_number] => 316584 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4395503 [patent_doc_number] => 06297156 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Method for enhanced filling of high aspect ratio dual damascene structures' [patent_app_type] => 1 [patent_app_number] => 9/314657 [patent_app_country] => US [patent_app_date] => 1999-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2946 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297156.pdf [firstpage_image] =>[orig_patent_app_number] => 314657 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4258273 [patent_doc_number] => 06204124 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Method for forming high density nonvolatile memories with high capacitive-coupling ratio' [patent_app_type] => 1 [patent_app_number] => 9/313084 [patent_app_country] => US [patent_app_date] => 1999-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2654 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/204/06204124.pdf [firstpage_image] =>[orig_patent_app_number] => 313084 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4188159 [patent_doc_number] => 06153468 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Method of forming a logic array for a decoder' [patent_app_type] => 1 [patent_app_number] => 9/313049 [patent_app_country] => US [patent_app_date] => 1999-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 9860 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/153/06153468.pdf [firstpage_image] =>[orig_patent_app_number] => 313049 [rel_patent_id] =>[rel_patent_doc_number] =>)