Search

Lalrinfamkim Hmar Malsawma

Examiner (ID: 2370)

Most Active Art Unit
2892
Art Unit(s)
2823, 2892, 2825
Total Applications
1951
Issued Applications
1709
Pending Applications
105
Abandoned Applications
179

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4155056 [patent_doc_number] => 06114198 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Method for forming a high surface area capacitor electrode for DRAM applications' [patent_app_type] => 1 [patent_app_number] => 9/307209 [patent_app_country] => US [patent_app_date] => 1999-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2343 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 342 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/114/06114198.pdf [firstpage_image] =>[orig_patent_app_number] => 307209 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/307209
Method for forming a high surface area capacitor electrode for DRAM applications May 6, 1999 Issued
Array ( [id] => 4155131 [patent_doc_number] => 06114204 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Method of fabricating high density flash memory with self-aligned tunneling window' [patent_app_type] => 1 [patent_app_number] => 9/306348 [patent_app_country] => US [patent_app_date] => 1999-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 2255 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/114/06114204.pdf [firstpage_image] =>[orig_patent_app_number] => 306348 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/306348
Method of fabricating high density flash memory with self-aligned tunneling window May 5, 1999 Issued
Array ( [id] => 4411664 [patent_doc_number] => 06172394 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Non-volatile semiconductor memory device having a floating gate with protruding conductive side-wall portions' [patent_app_type] => 1 [patent_app_number] => 9/302398 [patent_app_country] => US [patent_app_date] => 1999-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 24 [patent_no_of_words] => 6845 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/172/06172394.pdf [firstpage_image] =>[orig_patent_app_number] => 302398 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/302398
Non-volatile semiconductor memory device having a floating gate with protruding conductive side-wall portions Apr 29, 1999 Issued
Array ( [id] => 4297196 [patent_doc_number] => 06236076 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Ferroelectric field effect transistors for nonvolatile memory applications having functional gradient material' [patent_app_type] => 1 [patent_app_number] => 9/301867 [patent_app_country] => US [patent_app_date] => 1999-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 36 [patent_no_of_words] => 15601 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/236/06236076.pdf [firstpage_image] =>[orig_patent_app_number] => 301867 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/301867
Ferroelectric field effect transistors for nonvolatile memory applications having functional gradient material Apr 28, 1999 Issued
Array ( [id] => 1600460 [patent_doc_number] => 06475896 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument' [patent_app_type] => B1 [patent_app_number] => 09/117510 [patent_app_country] => US [patent_app_date] => 1999-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 69 [patent_no_of_words] => 11787 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/475/06475896.pdf [firstpage_image] =>[orig_patent_app_number] => 09117510 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/117510
Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument Apr 21, 1999 Issued
Array ( [id] => 6032995 [patent_doc_number] => 20020019099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-14 [patent_title] => 'SUPER SELF-ALIGNED TRENCH-GATE DMOS WITH REDUCED ON-RESISTANCE' [patent_app_type] => new [patent_app_number] => 09/296959 [patent_app_country] => US [patent_app_date] => 1999-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 62 [patent_figures_cnt] => 62 [patent_no_of_words] => 16916 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20020019099.pdf [firstpage_image] =>[orig_patent_app_number] => 09296959 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/296959
Super-self-aligned fabrication process of trench-gate DMOS with overlying device layer Apr 21, 1999 Issued
Array ( [id] => 4292432 [patent_doc_number] => 06268631 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Glass substrate assembly, semiconductor device and method of heat-treating glass substrate' [patent_app_type] => 1 [patent_app_number] => 9/294338 [patent_app_country] => US [patent_app_date] => 1999-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 8134 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/268/06268631.pdf [firstpage_image] =>[orig_patent_app_number] => 294338 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/294338
Glass substrate assembly, semiconductor device and method of heat-treating glass substrate Apr 19, 1999 Issued
Array ( [id] => 4354826 [patent_doc_number] => 06200877 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Method of forming a charge storage electrode having a selective hemispherical grains silicon film in a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/294348 [patent_app_country] => US [patent_app_date] => 1999-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 2849 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/200/06200877.pdf [firstpage_image] =>[orig_patent_app_number] => 294348 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/294348
Method of forming a charge storage electrode having a selective hemispherical grains silicon film in a semiconductor device Apr 19, 1999 Issued
Array ( [id] => 4357904 [patent_doc_number] => 06191022 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Fine pitch solder sphere placement' [patent_app_type] => 1 [patent_app_number] => 9/295101 [patent_app_country] => US [patent_app_date] => 1999-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2891 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/191/06191022.pdf [firstpage_image] =>[orig_patent_app_number] => 295101 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/295101
Fine pitch solder sphere placement Apr 17, 1999 Issued
Array ( [id] => 4358692 [patent_doc_number] => 06168986 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Method of making a sacrificial self-aligned interconnect structure' [patent_app_type] => 1 [patent_app_number] => 9/293369 [patent_app_country] => US [patent_app_date] => 1999-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 6649 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/168/06168986.pdf [firstpage_image] =>[orig_patent_app_number] => 293369 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/293369
Method of making a sacrificial self-aligned interconnect structure Apr 15, 1999 Issued
Array ( [id] => 4286313 [patent_doc_number] => 06211041 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Silicon-on-insulator (SOI) substrate and method of fabricating the same' [patent_app_type] => 1 [patent_app_number] => 9/292948 [patent_app_country] => US [patent_app_date] => 1999-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 12 [patent_no_of_words] => 8521 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/211/06211041.pdf [firstpage_image] =>[orig_patent_app_number] => 292948 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/292948
Silicon-on-insulator (SOI) substrate and method of fabricating the same Apr 15, 1999 Issued
Array ( [id] => 4357270 [patent_doc_number] => 06190978 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Method for fabricating lateral RF MOS devices with enhanced RF properties' [patent_app_type] => 1 [patent_app_number] => 9/293431 [patent_app_country] => US [patent_app_date] => 1999-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 6130 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/190/06190978.pdf [firstpage_image] =>[orig_patent_app_number] => 293431 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/293431
Method for fabricating lateral RF MOS devices with enhanced RF properties Apr 15, 1999 Issued
Array ( [id] => 4407212 [patent_doc_number] => 06238982 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Multiple threshold voltage semiconductor device fabrication technology' [patent_app_type] => 1 [patent_app_number] => 9/289909 [patent_app_country] => US [patent_app_date] => 1999-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 21 [patent_no_of_words] => 3115 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/238/06238982.pdf [firstpage_image] =>[orig_patent_app_number] => 289909 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/289909
Multiple threshold voltage semiconductor device fabrication technology Apr 12, 1999 Issued
Array ( [id] => 4139204 [patent_doc_number] => 06060357 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Method of manufacturing flash memory' [patent_app_type] => 1 [patent_app_number] => 9/286139 [patent_app_country] => US [patent_app_date] => 1999-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 2791 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/060/06060357.pdf [firstpage_image] =>[orig_patent_app_number] => 286139 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/286139
Method of manufacturing flash memory Apr 4, 1999 Issued
Array ( [id] => 4285931 [patent_doc_number] => 06211016 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Method for forming high density nonvolatile memories with high capacitive-coupling ratio' [patent_app_type] => 1 [patent_app_number] => 9/283406 [patent_app_country] => US [patent_app_date] => 1999-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2735 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/211/06211016.pdf [firstpage_image] =>[orig_patent_app_number] => 283406 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/283406
Method for forming high density nonvolatile memories with high capacitive-coupling ratio Mar 31, 1999 Issued
Array ( [id] => 4293957 [patent_doc_number] => 06184087 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Method for forming high density nonvolatile memories with high capacitive-coupling ratio' [patent_app_type] => 1 [patent_app_number] => 9/283405 [patent_app_country] => US [patent_app_date] => 1999-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2804 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184087.pdf [firstpage_image] =>[orig_patent_app_number] => 283405 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/283405
Method for forming high density nonvolatile memories with high capacitive-coupling ratio Mar 31, 1999 Issued
Array ( [id] => 7012538 [patent_doc_number] => 20010050391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-13 [patent_title] => 'CVD SOURCE MATERIAL FOR FORMING AN ELECTRODE, AND ELECTRODE AND WIRING FILM FOR CAPACITOR FORMED THEREFROM' [patent_app_type] => new [patent_app_number] => 09/277185 [patent_app_country] => US [patent_app_date] => 1999-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 8493 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20010050391.pdf [firstpage_image] =>[orig_patent_app_number] => 09277185 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/277185
CVD source material for forming an electrode, and electrode and wiring film for capacitor formed therefrom Mar 25, 1999 Issued
Array ( [id] => 4300337 [patent_doc_number] => 06181014 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Integrated circuit memory devices having highly integrated SOI memory cells therein' [patent_app_type] => 1 [patent_app_number] => 9/271519 [patent_app_country] => US [patent_app_date] => 1999-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 6033 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/181/06181014.pdf [firstpage_image] =>[orig_patent_app_number] => 271519 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/271519
Integrated circuit memory devices having highly integrated SOI memory cells therein Mar 17, 1999 Issued
Array ( [id] => 4294435 [patent_doc_number] => 06184119 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Methods for reducing semiconductor contact resistance' [patent_app_type] => 1 [patent_app_number] => 9/270123 [patent_app_country] => US [patent_app_date] => 1999-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 5949 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184119.pdf [firstpage_image] =>[orig_patent_app_number] => 270123 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/270123
Methods for reducing semiconductor contact resistance Mar 14, 1999 Issued
Array ( [id] => 4232866 [patent_doc_number] => 06117731 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Method of forming high capacitive-coupling ratio and high speed flash memories with a textured tunnel oxide' [patent_app_type] => 1 [patent_app_number] => 9/270908 [patent_app_country] => US [patent_app_date] => 1999-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 3346 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 428 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/117/06117731.pdf [firstpage_image] =>[orig_patent_app_number] => 270908 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/270908
Method of forming high capacitive-coupling ratio and high speed flash memories with a textured tunnel oxide Mar 14, 1999 Issued
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