Search

Lalrinfamkim Hmar Malsawma

Examiner (ID: 2370)

Most Active Art Unit
2892
Art Unit(s)
2823, 2892, 2825
Total Applications
1951
Issued Applications
1709
Pending Applications
105
Abandoned Applications
179

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4341181 [patent_doc_number] => 06333545 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-25 [patent_title] => 'Semiconductor device having blocking layer and fuses' [patent_app_type] => 1 [patent_app_number] => 9/256081 [patent_app_country] => US [patent_app_date] => 1999-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 49 [patent_no_of_words] => 12840 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/333/06333545.pdf [firstpage_image] =>[orig_patent_app_number] => 256081 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/256081
Semiconductor device having blocking layer and fuses Feb 23, 1999 Issued
Array ( [id] => 4232570 [patent_doc_number] => 06117712 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Method of forming ultra-short channel and elevated S/D MOSFETS with a metal gate on SOI substrate' [patent_app_type] => 1 [patent_app_number] => 9/248955 [patent_app_country] => US [patent_app_date] => 1999-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 3095 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/117/06117712.pdf [firstpage_image] =>[orig_patent_app_number] => 248955 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/248955
Method of forming ultra-short channel and elevated S/D MOSFETS with a metal gate on SOI substrate Feb 11, 1999 Issued
Array ( [id] => 7645714 [patent_doc_number] => 06472255 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Solid-state imaging device and method of its production' [patent_app_type] => B1 [patent_app_number] => 09/243440 [patent_app_country] => US [patent_app_date] => 1999-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 5825 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 12 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/472/06472255.pdf [firstpage_image] =>[orig_patent_app_number] => 09243440 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/243440
Solid-state imaging device and method of its production Feb 2, 1999 Issued
Array ( [id] => 4258187 [patent_doc_number] => 06258621 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Method of fabricating a semiconductor device having insulating tape interposed between chip and chip support' [patent_app_type] => 1 [patent_app_number] => 9/240612 [patent_app_country] => US [patent_app_date] => 1999-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 3550 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/258/06258621.pdf [firstpage_image] =>[orig_patent_app_number] => 240612 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/240612
Method of fabricating a semiconductor device having insulating tape interposed between chip and chip support Jan 31, 1999 Issued
Array ( [id] => 4358042 [patent_doc_number] => 06255157 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Method for forming a ferroelectric capacitor under the bit line' [patent_app_type] => 1 [patent_app_number] => 9/238853 [patent_app_country] => US [patent_app_date] => 1999-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2750 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255157.pdf [firstpage_image] =>[orig_patent_app_number] => 238853 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/238853
Method for forming a ferroelectric capacitor under the bit line Jan 26, 1999 Issued
Array ( [id] => 4155028 [patent_doc_number] => 06114196 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Method of fabricating metal-oxide semiconductor transistor' [patent_app_type] => 1 [patent_app_number] => 9/227959 [patent_app_country] => US [patent_app_date] => 1999-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1472 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/114/06114196.pdf [firstpage_image] =>[orig_patent_app_number] => 227959 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/227959
Method of fabricating metal-oxide semiconductor transistor Jan 10, 1999 Issued
Array ( [id] => 4357744 [patent_doc_number] => 06255136 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Method of making electronic package with compressible heatsink structure' [patent_app_type] => 1 [patent_app_number] => 9/225191 [patent_app_country] => US [patent_app_date] => 1999-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 6552 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255136.pdf [firstpage_image] =>[orig_patent_app_number] => 225191 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/225191
Method of making electronic package with compressible heatsink structure Jan 4, 1999 Issued
Array ( [id] => 4287038 [patent_doc_number] => 06268276 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Area array air gap structure for intermetal dielectric application' [patent_app_type] => 1 [patent_app_number] => 9/216823 [patent_app_country] => US [patent_app_date] => 1998-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 1889 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/268/06268276.pdf [firstpage_image] =>[orig_patent_app_number] => 216823 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/216823
Area array air gap structure for intermetal dielectric application Dec 20, 1998 Issued
Array ( [id] => 4381201 [patent_doc_number] => 06277707 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Method of manufacturing semiconductor device having a recessed gate structure' [patent_app_type] => 1 [patent_app_number] => 9/212931 [patent_app_country] => US [patent_app_date] => 1998-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 8278 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/277/06277707.pdf [firstpage_image] =>[orig_patent_app_number] => 212931 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/212931
Method of manufacturing semiconductor device having a recessed gate structure Dec 15, 1998 Issued
Array ( [id] => 4348805 [patent_doc_number] => 06214742 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Post-via tin removal for via resistance improvement' [patent_app_type] => 1 [patent_app_number] => 9/206513 [patent_app_country] => US [patent_app_date] => 1998-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 3546 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/214/06214742.pdf [firstpage_image] =>[orig_patent_app_number] => 206513 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/206513
Post-via tin removal for via resistance improvement Dec 6, 1998 Issued
Array ( [id] => 4290399 [patent_doc_number] => 06235639 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Method of making straight wall containers and the resultant containers' [patent_app_type] => 1 [patent_app_number] => 9/200153 [patent_app_country] => US [patent_app_date] => 1998-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4024 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/235/06235639.pdf [firstpage_image] =>[orig_patent_app_number] => 200153 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/200153
Method of making straight wall containers and the resultant containers Nov 24, 1998 Issued
Array ( [id] => 4242630 [patent_doc_number] => 06144074 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Semiconductor memory device having stack-type memory cells and a method for manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/196548 [patent_app_country] => US [patent_app_date] => 1998-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 6052 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/144/06144074.pdf [firstpage_image] =>[orig_patent_app_number] => 196548 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/196548
Semiconductor memory device having stack-type memory cells and a method for manufacturing the same Nov 19, 1998 Issued
Array ( [id] => 4232894 [patent_doc_number] => 06117733 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Poly tip formation and self-align source process for split-gate flash cell' [patent_app_type] => 1 [patent_app_number] => 9/193670 [patent_app_country] => US [patent_app_date] => 1998-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 27 [patent_no_of_words] => 6934 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 394 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/117/06117733.pdf [firstpage_image] =>[orig_patent_app_number] => 193670 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/193670
Poly tip formation and self-align source process for split-gate flash cell Nov 16, 1998 Issued
Array ( [id] => 1141551 [patent_doc_number] => 06777320 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-17 [patent_title] => 'In-plane on-chip decoupling capacitors and method for making same' [patent_app_type] => B1 [patent_app_number] => 09/191930 [patent_app_country] => US [patent_app_date] => 1998-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 21 [patent_no_of_words] => 4888 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/777/06777320.pdf [firstpage_image] =>[orig_patent_app_number] => 09191930 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/191930
In-plane on-chip decoupling capacitors and method for making same Nov 12, 1998 Issued
Array ( [id] => 4116867 [patent_doc_number] => 06071790 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Method of crown capacitor rounding by oxidant dipping process' [patent_app_type] => 1 [patent_app_number] => 9/185629 [patent_app_country] => US [patent_app_date] => 1998-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1871 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/071/06071790.pdf [firstpage_image] =>[orig_patent_app_number] => 185629 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/185629
Method of crown capacitor rounding by oxidant dipping process Nov 3, 1998 Issued
Array ( [id] => 4297407 [patent_doc_number] => 06236087 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'SCR cell for electrical overstress protection of electronic circuits' [patent_app_type] => 1 [patent_app_number] => 9/184924 [patent_app_country] => US [patent_app_date] => 1998-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 7987 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/236/06236087.pdf [firstpage_image] =>[orig_patent_app_number] => 184924 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/184924
SCR cell for electrical overstress protection of electronic circuits Nov 1, 1998 Issued
Array ( [id] => 4301381 [patent_doc_number] => 06198145 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Method for manufacturing a semiconductor material integrated microactuator, in particular for a hard disc mobile read/write head, and a microactuator obtained thereby' [patent_app_type] => 1 [patent_app_number] => 9/181717 [patent_app_country] => US [patent_app_date] => 1998-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3398 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/198/06198145.pdf [firstpage_image] =>[orig_patent_app_number] => 181717 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/181717
Method for manufacturing a semiconductor material integrated microactuator, in particular for a hard disc mobile read/write head, and a microactuator obtained thereby Oct 27, 1998 Issued
Array ( [id] => 4357948 [patent_doc_number] => 06255150 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Use of crystalline SiOx barriers for Si-based resonant tunneling diodes' [patent_app_type] => 1 [patent_app_number] => 9/178250 [patent_app_country] => US [patent_app_date] => 1998-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 2123 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255150.pdf [firstpage_image] =>[orig_patent_app_number] => 178250 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/178250
Use of crystalline SiOx barriers for Si-based resonant tunneling diodes Oct 22, 1998 Issued
Array ( [id] => 4130061 [patent_doc_number] => 06033955 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Method of making flexibly partitioned metal line segments for a simultaneous operation flash memory device with a flexible bank partition architecture' [patent_app_type] => 1 [patent_app_number] => 9/159023 [patent_app_country] => US [patent_app_date] => 1998-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 7015 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/033/06033955.pdf [firstpage_image] =>[orig_patent_app_number] => 159023 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/159023
Method of making flexibly partitioned metal line segments for a simultaneous operation flash memory device with a flexible bank partition architecture Sep 22, 1998 Issued
Array ( [id] => 4130885 [patent_doc_number] => 06146939 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Metal-polycrystalline silicon-N-well multiple layered capacitor' [patent_app_type] => 1 [patent_app_number] => 9/156358 [patent_app_country] => US [patent_app_date] => 1998-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3814 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/146/06146939.pdf [firstpage_image] =>[orig_patent_app_number] => 156358 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/156358
Metal-polycrystalline silicon-N-well multiple layered capacitor Sep 17, 1998 Issued
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