Search

Lam T. Mai

Examiner (ID: 13914)

Most Active Art Unit
2845
Art Unit(s)
2819, 2845
Total Applications
2568
Issued Applications
2446
Pending Applications
84
Abandoned Applications
75

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 747561 [patent_doc_number] => 07026876 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-11 [patent_title] => 'High linearity smart HBT power amplifiers for CDMA/WCDMA application' [patent_app_type] => utility [patent_app_number] => 10/782598 [patent_app_country] => US [patent_app_date] => 2004-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3378 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/026/07026876.pdf [firstpage_image] =>[orig_patent_app_number] => 10782598 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/782598
High linearity smart HBT power amplifiers for CDMA/WCDMA application Feb 17, 2004 Issued
Array ( [id] => 7609280 [patent_doc_number] => 06998909 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-02-14 [patent_title] => 'Method to compensate for memory effect in lookup table based digital predistorters' [patent_app_type] => utility [patent_app_number] => 10/781082 [patent_app_country] => US [patent_app_date] => 2004-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8098 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 14 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/998/06998909.pdf [firstpage_image] =>[orig_patent_app_number] => 10781082 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/781082
Method to compensate for memory effect in lookup table based digital predistorters Feb 16, 2004 Issued
Array ( [id] => 726744 [patent_doc_number] => 07046177 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-16 [patent_title] => 'Servo system, apparatus comprising a servo system, sigma delta modulator, and integrated circuit comprising a sigma delta modulator' [patent_app_type] => utility [patent_app_number] => 10/544199 [patent_app_country] => US [patent_app_date] => 2004-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4229 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/046/07046177.pdf [firstpage_image] =>[orig_patent_app_number] => 10544199 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/544199
Servo system, apparatus comprising a servo system, sigma delta modulator, and integrated circuit comprising a sigma delta modulator Feb 5, 2004 Issued
Array ( [id] => 538814 [patent_doc_number] => 07180435 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-20 [patent_title] => 'Low-complexity sampling rate conversion method and apparatus for audio processing' [patent_app_type] => utility [patent_app_number] => 10/768060 [patent_app_country] => US [patent_app_date] => 2004-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 10695 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/180/07180435.pdf [firstpage_image] =>[orig_patent_app_number] => 10768060 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/768060
Low-complexity sampling rate conversion method and apparatus for audio processing Feb 1, 2004 Issued
Array ( [id] => 7003045 [patent_doc_number] => 20050168358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'METHOD AND APPARATUS FOR CODED SYMBOL STUFFING IN RECORDING SYSTEMS' [patent_app_type] => utility [patent_app_number] => 10/767831 [patent_app_country] => US [patent_app_date] => 2004-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9208 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20050168358.pdf [firstpage_image] =>[orig_patent_app_number] => 10767831 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/767831
Method and apparatus for coded symbol stuffing in recording systems Jan 28, 2004 Issued
Array ( [id] => 969163 [patent_doc_number] => 06940438 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-06 [patent_title] => 'Method and circuit for reducing quantizer input/output swing in a sigma-delta modulator' [patent_app_type] => utility [patent_app_number] => 10/766233 [patent_app_country] => US [patent_app_date] => 2004-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 4395 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/940/06940438.pdf [firstpage_image] =>[orig_patent_app_number] => 10766233 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/766233
Method and circuit for reducing quantizer input/output swing in a sigma-delta modulator Jan 27, 2004 Issued
Array ( [id] => 7364999 [patent_doc_number] => 20040217896 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-04 [patent_title] => 'Multistage analog-to-digital converter' [patent_app_type] => new [patent_app_number] => 10/764133 [patent_app_country] => US [patent_app_date] => 2004-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3718 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20040217896.pdf [firstpage_image] =>[orig_patent_app_number] => 10764133 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/764133
Multistage analog-to-digital converter Jan 22, 2004 Issued
Array ( [id] => 7619478 [patent_doc_number] => 06943709 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-13 [patent_title] => 'Self-adaptable data compression technique' [patent_app_type] => utility [patent_app_number] => 10/755753 [patent_app_country] => US [patent_app_date] => 2004-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 23 [patent_no_of_words] => 5206 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/943/06943709.pdf [firstpage_image] =>[orig_patent_app_number] => 10755753 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/755753
Self-adaptable data compression technique Jan 11, 2004 Issued
Array ( [id] => 412407 [patent_doc_number] => 07283070 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-10-16 [patent_title] => 'Dynamic calibration of I/O power supply level' [patent_app_type] => utility [patent_app_number] => 10/741680 [patent_app_country] => US [patent_app_date] => 2003-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2687 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/283/07283070.pdf [firstpage_image] =>[orig_patent_app_number] => 10741680 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/741680
Dynamic calibration of I/O power supply level Dec 18, 2003 Issued
Array ( [id] => 986043 [patent_doc_number] => 06924759 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-02 [patent_title] => 'Multi-channel integrated circuit comprising a plurality of DACs, and a method for monitoring the output of the DACs' [patent_app_type] => utility [patent_app_number] => 10/731334 [patent_app_country] => US [patent_app_date] => 2003-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 11 [patent_no_of_words] => 4137 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/924/06924759.pdf [firstpage_image] =>[orig_patent_app_number] => 10731334 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/731334
Multi-channel integrated circuit comprising a plurality of DACs, and a method for monitoring the output of the DACs Dec 8, 2003 Issued
Array ( [id] => 617070 [patent_doc_number] => 07145483 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-05 [patent_title] => 'Chip to chip interface for encoding data and clock signals' [patent_app_type] => utility [patent_app_number] => 10/730443 [patent_app_country] => US [patent_app_date] => 2003-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10735 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/145/07145483.pdf [firstpage_image] =>[orig_patent_app_number] => 10730443 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/730443
Chip to chip interface for encoding data and clock signals Dec 7, 2003 Issued
Array ( [id] => 617071 [patent_doc_number] => 07145484 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-05 [patent_title] => 'Digital signal processing method, processor thereof, program thereof, and recording medium containing the program' [patent_app_type] => utility [patent_app_number] => 10/535708 [patent_app_country] => US [patent_app_date] => 2003-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 56 [patent_no_of_words] => 21772 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/145/07145484.pdf [firstpage_image] =>[orig_patent_app_number] => 10535708 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/535708
Digital signal processing method, processor thereof, program thereof, and recording medium containing the program Nov 19, 2003 Issued
Array ( [id] => 1087009 [patent_doc_number] => 06831576 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-14 [patent_title] => 'A/D converter with improved resolution by sampling a superposed signal' [patent_app_type] => B2 [patent_app_number] => 10/713335 [patent_app_country] => US [patent_app_date] => 2003-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2445 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/831/06831576.pdf [firstpage_image] =>[orig_patent_app_number] => 10713335 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/713335
A/D converter with improved resolution by sampling a superposed signal Nov 12, 2003 Issued
Array ( [id] => 994241 [patent_doc_number] => 06917312 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-12 [patent_title] => 'Technique for improving the quality of digital signals in a multi-level signaling system' [patent_app_type] => utility [patent_app_number] => 10/703631 [patent_app_country] => US [patent_app_date] => 2003-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 42 [patent_no_of_words] => 14976 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/917/06917312.pdf [firstpage_image] =>[orig_patent_app_number] => 10703631 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/703631
Technique for improving the quality of digital signals in a multi-level signaling system Nov 9, 2003 Issued
Array ( [id] => 1019233 [patent_doc_number] => 06891485 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-10 [patent_title] => 'Interspersed training for turbo coded modulation' [patent_app_type] => utility [patent_app_number] => 10/703286 [patent_app_country] => US [patent_app_date] => 2003-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 10376 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/891/06891485.pdf [firstpage_image] =>[orig_patent_app_number] => 10703286 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/703286
Interspersed training for turbo coded modulation Nov 6, 2003 Issued
Array ( [id] => 1003181 [patent_doc_number] => 06909392 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-21 [patent_title] => 'Analog to digital converter using multiple staggered successive approximation cells' [patent_app_type] => utility [patent_app_number] => 10/694759 [patent_app_country] => US [patent_app_date] => 2003-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 1696 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/909/06909392.pdf [firstpage_image] =>[orig_patent_app_number] => 10694759 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/694759
Analog to digital converter using multiple staggered successive approximation cells Oct 28, 2003 Issued
Array ( [id] => 7170310 [patent_doc_number] => 20050122244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'Digital signal processing device and audio signal reproduction device' [patent_app_type] => utility [patent_app_number] => 10/507832 [patent_app_country] => US [patent_app_date] => 2003-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7275 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20050122244.pdf [firstpage_image] =>[orig_patent_app_number] => 10507832 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/507832
Digital signal processing device and audio signal reproduction device Oct 22, 2003 Issued
Array ( [id] => 7222750 [patent_doc_number] => 20040155806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-12 [patent_title] => 'SYNCHRONIZING CIRCUITS AND METHODS FOR PARALLEL PATH ANALOG-TO-DIGITAL CONVERTERS' [patent_app_type] => new [patent_app_number] => 10/689435 [patent_app_country] => US [patent_app_date] => 2003-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3929 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20040155806.pdf [firstpage_image] =>[orig_patent_app_number] => 10689435 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/689435
Synchronizing circuits and methods for parallel path analog-to-digital converters Oct 19, 2003 Issued
Array ( [id] => 7437382 [patent_doc_number] => 20040066320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-08 [patent_title] => 'Multi-stage pipeline type analog-to-digital conversion circuit for adjusting input signals' [patent_app_type] => new [patent_app_number] => 10/673137 [patent_app_country] => US [patent_app_date] => 2003-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9232 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20040066320.pdf [firstpage_image] =>[orig_patent_app_number] => 10673137 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/673137
Multi-stage pipeline type analog-to-digital conversion circuit for adjusting input signals Sep 29, 2003 Issued
Array ( [id] => 7309483 [patent_doc_number] => 20040117712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-17 [patent_title] => 'Frequency mapped coding for signal error correction' [patent_app_type] => new [patent_app_number] => 10/676053 [patent_app_country] => US [patent_app_date] => 2003-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 2979 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20040117712.pdf [firstpage_image] =>[orig_patent_app_number] => 10676053 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/676053
Frequency mapped coding for signal error correction Sep 29, 2003 Issued
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